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| motorola.com/semiconductors m68hc08 microcontrollers mc68hc908mr32/d rev. 6.0 mc68hc908mr32 data sheet 11/2003 mc68HC908MR16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 ? mc68HC908MR16 ? rev. 6.0 data sheet motorola 3 motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. this product incorporates superflash? technol ogy licensed from sst. ? motorola, inc., 2003 mc68hc908mr32 mc68HC908MR16 data sheet to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://motorola.com/semiconductors the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . revision history data sheet mc68hc908mr32 ? mc68HC908MR16 ? rev. 6.0 4 revision history motorola revision history date revision level description page number(s) august, 2001 3.0 figure 2-1. mc68hc908mr32 memory map ? added flash block protect register (flbpr) at address location $ff7e 29 figure a-1. mc68HC908MR16 memory map ? added flash block protect register (flbpr) at address location $ff7e 306 october, 2001 4.0 3.3.3 conversion time ? reworked equations and text for clarity. 50 december, 2001 5.0 figure 18-8. monitor mode circuit ? pta7 and connecting circuitry added 279 table 18-2. monitor mode signal requirements and options ? switch locations added to column headings for clarity 281 section 16. timer interface a (tima) ? timer discrepancies corrected throughout this section. 233 section 17. timer interface b (timb) ? timer discrepancies corrected throughout this section. 255 november, 2003 6.0 reformatted to meet current publication standards throughout 2.8.2 flash page erase operation ? procedure reworked for clarity 42 2.8.3 flash mass erase operation ? procedure reworked for clarity 42 2.8.4 flash prog ram operation ? procedure reworked for clarity 43 figure 14-14. sim break status register (sbsr) ? clarified definition of sbsw bit. 207 19.5 dc electrical characteristics ? corrected maximum va lue for monitor mode entry voltage (on irq ) 291 19.6 flash memory characteristics ? updated table entries 292 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola list of sections 5 data sheet ? mc68hc 908mr32 mc68HC908MR16 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 section 3. analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . 47 section 4. clock generator m odule (cgm). . . . . . . . . . . . . . . . . . . . . . 59 section 5. configuration regi ster (config) . . . . . . . . . . . . . . . . . . . . 79 section 6. computer operat ing properly (cop) . . . . . . . . . . . . . . . . . 83 section 7. central processor un it (cpu) . . . . . . . . . . . . . . . . . . . . . . . 87 section 8. external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 section 9. low-voltage inhibit (lvi) . . . . . . . . . . . . . . . . . . . . . . . . . . 107 section 10. input/output (i/o) ports (ports ) . . . . . . . . . . . . . . . . . . 111 section 11. power-on reset (p or) . . . . . . . . . . . . . . . . . . . . . . . . . . .125 section 12. pulse-widt h modulator for motor control (pwmmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 section 13. serial communications in terface module (sci) . . . . . . . 169 section 14. system integrat ion module (sim) . . . . . . . . . . . . . . . . . . 195 section 15. serial peripheral interface m odule (spi). . . . . . . . . . . . . 209 section 16. timer interface a (tima) . . . . . . . . . . . . . . . . . . . . . . . . . 233 section 17. timer interface b (timb) . . . . . . . . . . . . . . . . . . . . . . . . . 255 section 18. development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 section 19. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 289 section 20. ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 appendix a. mc68hc908mr1 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola table of contents 7 data sheet ? mc68hc 908mr32 mc68HC908MR16 table of contents section 1. gener al description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.5 cgm power supply pins (v dda and v ssad ) . . . . . . . . . . . . . . . . . . 25 1.4.6 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . 25 1.4.7 analog power supply pins (v ddad and v ssad ) . . . . . . . . . . . . . . . . 25 1.4.8 adc voltage decoupling capacitor pin (v refh ) . . . . . . . . . . . . . . . 25 1.4.9 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . . . . . . . 25 1.4.10 port a input/output (i/o) pins (pta7? pta0) . . . . . . . . . . . . . . . . . . 25 1.4.11 port b i/o pins (ptb7/atd7?ptb0/atd0) . . . . . . . . . . . . . . . . . . . 25 1.4.12 port c i/o pins (ptc6?ptc2 and ptc1/atd9?ptc0/atd8) . . . . . 25 1.4.13 port d input-only pins (ptd6/is3 ?ptd4/is1 and ptd3/fault4?ptd0/fault1) . . . . . . . . . . . . . . . . . . . . . . 26 1.4.14 pwm pins (pwm6?pwm1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.15 pwm ground pin (pwmgnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.16 port e i/o pins (pte7/tch3a?pte3/tclka and pte2/tch1b?pte0/tclkb) . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4.17 port f i/o pins (ptf5/txd?ptf4/rxd and ptf3/miso?ptf0/spsck) . . . . . . . . . . . . . . . . . . . . . . . . . 26 section 2. memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.7 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 8 table of contents motorola 2.8 flash memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.8.1 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.2 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.8.3 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.8.4 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.8.5 flash block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.8.6 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.8.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.8.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 section 3. anal og-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.1 adc port i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.3 conversion time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.5 result justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.6 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.1 adc analog power pin (v ddad ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.2 adc analog ground pin (v ssad ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.3 adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . . . . . . . 53 3.6.5 adc voltage in (advin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.6 adc external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.6.1 v refh and v refl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.6.2 anx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.6.3 grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.7.2 adc data register high. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.7.3 adc data register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.7.4 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola table of contents 9 section 4. clock g enerator module (cgm) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.1 crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.2 phase-locked loop circuit (pll). . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.2.3 manual and automatic pll bandwidth modes . . . . . . . . . . . . . . . 62 4.3.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.2.5 special programming exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3.3 base clock selector circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3.4 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4.1 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4.2 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4.3 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . . . 67 4.4.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4.5 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . 67 4.4.6 crystal output frequency signal (cgmxclk). . . . . . . . . . . . . . . . . 68 4.4.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.8 cgm cpu interrupt (cgmint). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.5 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.5.1 pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.5.2 pll bandwidth control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5.3 pll programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.7 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.8 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.8.1 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.8.2 parametric influences on reaction time . . . . . . . . . . . . . . . . . . . . . 75 4.8.3 choosing a filter capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.8.4 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 section 5. configurat ion register (config) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 10 table of contents motorola section 6. computer o perating properly (cop) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.3 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.6 copd (cop disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.7 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 section 7. central processor un it (cpu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3.2 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 section 8. external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola table of contents 11 section 9. low-volt age inhibit (lvi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.1 polled lvi operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.4 lvi trip selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.4 lvi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.6 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.7 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 section 10. input/output (i/o) ports (ports) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 10.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.2.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.4 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.6.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.7 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.7.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.7.2 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 section 11. power-on reset (por) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 12 table of contents motorola section 12. pul se-width modulator for motor control (pwmmc) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.3 timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.3.1 resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.3.2 prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.4 pwm generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.4.1 load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.4.2 pwm data overflow and underflow conditions . . . . . . . . . . . . . . . 137 12.5 output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.5.1 selecting six independent pwms or three complementary pwm pairs . . . . . . . . . . . . . . . . . . . . 138 12.5.2 dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.5.3 top/bottom correction with motor phase current polarity sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.5.4 output polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5.5 pwm output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.6 fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6.1 fault condition input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.6.1.1 fault pin filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.6.1.2 automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.6.1.3 manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.6.2 software output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.6.3 output port control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.7 initialization and the pwmen bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.8 pwm operation in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.9 control logic block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.9.1 pwm counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.9.2 pwm counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.9.3 pwmx value registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.9.4 pwm control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.9.5 pwm control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.9.6 dead-time write-once register . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.9.7 pwm disable mapping write-once register . . . . . . . . . . . . . . . . . 162 12.9.8 fault control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.9.9 fault status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.9.10 fault acknowledge register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.9.11 pwm output control regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.10 pwm glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola table of contents 13 section 13. serial communications interface module (sci) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.3.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.3.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.3.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.3.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.3.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.3.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.3.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.3.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.3.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.3.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.3.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.3.3.3 data sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.3.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.3.3.5 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.3.3.6 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 13.3.3.7 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.5 sci during break module interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.6.1 ptf5/txd (transmit data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.6.2 ptf4/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.7.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.7.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13.7.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 13.7.4 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13.7.5 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.7.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.7.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 section 14. system in tegration module (sim) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . 197 14.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . 197 14.2.3 clocks in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 14 table of contents motorola 14.3 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.3.2 active resets from internal sources . . . . . . . . . . . . . . . . . . . . . . . 199 14.3.2.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . 200 14.3.2.3 illegal opcode reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.3.2.5 forced monitor mode entry reset (m enrst) . . . . . . . . . . . . . . 201 14.3.2.6 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.4 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . 202 14.4.2 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.5 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.5.1 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.5.1.2 software interrupt (swi) instruction . . . . . . . . . . . . . . . . . . . . . . 205 14.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.6 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.6.1 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 14.7.1 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . 208 section 15. serial peripheral interface module (spi) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 15.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 15.4.1 master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 15.4.2 slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 15.5 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 15.5.1 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . 214 15.5.2 transmission format when cpha = 0. . . . . . . . . . . . . . . . . . . . . . 215 15.5.3 transmission format when cpha = 1. . . . . . . . . . . . . . . . . . . . . . 216 15.5.4 transmission initiation lat ency . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 15.6.1 overflow error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 15.6.2 mode fault error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.8 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola table of contents 15 15.9 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.10 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 15.11 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.11.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 15.11.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.11.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.11.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 15.11.5 v ss (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.12 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.12.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.12.2 spi status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . 229 15.12.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 section 16. timer interface a (tima) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 16.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.3.1 tima counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.3.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.3.3.1 unbuffered output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.3.4 pulse-width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.3.4.1 unbuffered pwm signal generation. . . . . . . . . . . . . . . . . . . . . . 241 16.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . 242 16.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.5 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.6.1 tima clock pin (pte3/tclka) . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.6.2 tima channel i/o pins (pte4/tch0a?pte7/tch3a) . . . . . . . . . 245 16.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 16.7.1 tima status and control register . . . . . . . . . . . . . . . . . . . . . . . . . 245 16.7.2 tima counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 16.7.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . 248 16.7.4 tima channel status and control registers . . . . . . . . . . . . . . . . . 248 16.7.5 tima channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 16 table of contents motorola section 17. timer interface b (timb) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.3.1 timb counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 17.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 17.3.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 17.3.3.1 unbuffered output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 17.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 17.3.4 pulse-width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.3.4.1 unbuffered pwm signal generation. . . . . . . . . . . . . . . . . . . . . . 262 17.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . 262 17.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 17.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 17.5 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 17.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 17.6.1 timb clock pin (pte0/tclkb) . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 17.6.2 timb channel i/o pins (pte1/tch0b?pte2/tch1b) . . . . . . . . . 265 17.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 17.7.1 timb status and control register . . . . . . . . . . . . . . . . . . . . . . . . . 265 17.7.2 timb counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 17.7.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . 268 17.7.4 timb channel status and control registers . . . . . . . . . . . . . . . . . 268 17.7.5 timb channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 section 18. development support 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.2 break module (brk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 18.2.1.1 flag protection during break interrupt s . . . . . . . . . . . . . . . . . . . 275 18.2.1.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.2.1.3 tim1 and tim2 during break interrupts . . . . . . . . . . . . . . . . . . . 275 18.2.1.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.2.2 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.2.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.2.2.2 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.2.3 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 18.2.3.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . 276 18.2.3.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 18.2.3.3 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 18.2.3.4 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola table of contents 17 18.3 monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.3.1.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 18.3.1.2 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 18.3.1.3 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.3.1.4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 18.3.1.5 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.3.1.6 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.3.1.7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18.3.1.8 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 18.3.2 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 section 19. electri cal specifications 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 19.3 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 19.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 19.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 19.6 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 19.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 19.8 serial peripheral interface characteristics . . . . . . . . . . . . . . . . . . . . . . 294 19.9 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . 297 19.10 clock generation module component specifications . . . . . . . . . . . . . 297 19.11 cgm operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19.12 cgm acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . 298 19.13 analog-to-digital converter (adc) characte ristics. . . . . . . . . . . . . . . . 299 section 20. ordering information and mechanical specifications 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 20.2 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 20.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . . . . . . . . 302 20.4 56-pin shrink dual in-line package (sdip) . . . . . . . . . . . . . . . . . . . . . 303 appendix a. mc68HC908MR16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 18 table of contents motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola general description 19 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 1. general description 1.1 introduction the mc68hc908mr32 is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (m cus). all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory si zes and types, and package types. the information contained in this docum ent pertains to the mc68HC908MR16 with the exceptions shown in appendix a. mc68HC908MR16 . 1.2 features features include: high-performance m68hc08 architecture fully upward-compatible object co de with m6805, m146805, and m68hc05 families 8-mhz internal bus frequency on-chip flash memory with in-circuit programming capabilities of flash program memory: mc68hc908mr32 ? 32 kbytes mc68HC908MR16 ? 16 kbytes on-chip programming firmware fo r use with host personal computer flash data security (1) 768 bytes of on-chip random-access memory (ram) 12-bit, 6-channel center-aligned or edge-aligned pulse-width modulator (pwmmc) serial peripheral interface module (spi) serial communications interface module (sci) 16-bit, 4-channel timer interface module (tima) 16-bit, 2-channel timer interface module (timb) 1. no security feature is absolutely secure. ho wever, motorola?s strat egy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 20 general description motorola clock generator module (cgm) low-voltage inhibit (lvi) module with software selectable trip points 10-bit, 10-channel analog-to-digital converter (adc) system protection features: ? optional computer operating properly (cop) reset ? low-voltage detection with optional reset ? illegal opcode or address dete ction with optional reset ? fault detection with optional pwm disabling available packages: ? 64-pin plastic quad flat pack (qfp) ? 56-pin shrink dual in-line package (sdip) low-power design, fully static with wait mode master reset pin (rst ) and power-on reset (por) stop mode as an option break module (brk) supports setting the in-circuit simulator (ics) single break point features of the cpu08 include: enhanced m68hc05 programming model extensive loop control functions 16 addressing modes (eight more than the m68hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications c language support 1.3 mcu bl ock diagram figure 1-1 shows the structure of the mc68hc908mr32. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 data sheet ? rev. 6.0 motorola general description 21 general description mcu block diagram figure 1-1. mcu block diagram clock generator module system integration module serial communications interface module serial peripheral interface module (2) timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 112 bytes user flash ? 32,256 bytes user ram ? 768 bytes monitor rom ? 240 bytes user flash vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq v ss v dd v ddad pta7?pta0 pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b (1) pte1/tch0b (1) pte0/tclkb (1) ptf5/txd ptf4/rxd ptf3/miso (1) ptf2/mosi (1) ptf1/ss (1) ptf0/spsck (1) timer interface module b pulse-width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9 (1) ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssad v ddad v ssad (3) pwmgnd v refl (3) v refh notes: 1. these pins are not avail able in the 56-pin sdip package. 2. this module is not avail able in the 56-pin sdip package. 3. in the 56-pin sdip package, these pins are bonded together. single break module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 22 general description motorola 1.4 pin assignments figure 1-2 shows the 64-pin qfp pin assignments and figure 1-3 shows the 56-pin sdip pin assignments. figure 1-2. 64-pin qfp pin assignments ptc1/atd9 pta2 v ss ptc0/atd8 ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 v ddad v ssad v refl v refh ptc2 ptc3 ptc4 ptc5 irq ptf5/txd ptf4/rxd ptf3/miso ptf2/mosi ptf1/ss ptf0/spsck v dd pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b pte1/tch0b pta1 pta0 v ssad osc2 osc1 cgmxfc v ddad rst ptb1/atd1 ptb0/atd0 pta7 pta6 pta5 pta4 pta3 ptd1/fault2 ptc6 ptd0/fault1 ptd2/fault3 ptd3/fault4 ptd4/is1 ptd5/is2 ptd6/is3 pwm1 pwm2 pwm3 pwm4 pte0/tclkb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pwmgnd pwm5 pwm6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola general description 23 figure 1-3. 56-pin sdip pin assignments pta2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pta3 pta4 pta5 pta6 pta7 ptb0/atd0 ptb1/atd1 ptb2/atd2 ptb3/atd3 ptb4/atd4 ptb5/atd5 ptb6/atd5 ptb7/atd7 ptc0/atd8 v ddad v ssad /v refl v refh ptc2 ptc3 ptc4 ptc5 ptc6 ptd0/fault1 ptd1/fault2 ptd2/fault3 ptd3/fault4 ptd4/is1 ptd5/is2 ptd6/is3 pwm1 pwm2 pwm3 pwm4 pwmgnd pwm5 pwm6 nc pte3/tclka pte4/tch0a pte5/tch1a pte6/tch2a pte7/tch3a v dd v ss ptf4/rxd ptf5/txd irq rst v dda cgmxfc osc1 osc2 v ssa pta0 pta1 note: ptc1, pte0, pte1, pte2, pt f0, ptf1, ptf2, and ptf3 are removed from this package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 24 general description motorola 1.4.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins plac e high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high-current levels. figure 1-4. power supply bypassing 1.4.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. for more detailed information, see section 4. clock generator module (cgm) . 1.4.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire sy stem. it is driven low when any internal reset source is asserted. see section 14. system integration module (sim) . 1.4.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. see section 8. external interrupt (irq) . mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown r epresent typical applications. 1?10 f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola general description 25 1.4.5 cgm power supply pins (v dda and v ssad ) v dda and v ssad are the power supply pins for the analog portion of the clock generator module (cgm). decoupling of these pins should be per the digital supply. see section 4. clock generator module (cgm) . 1.4.6 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capac itor connection for the cgm. see section 4. clock generator module (cgm) . 1.4.7 analog power supply pins (v ddad and v ssad ) v ddad and v ssad are the power supply pins for the analog-to-digital converter. decoupling of these pins should be per the digital supply. see section 3. analog-to-digital converter (adc) . 1.4.8 adc voltage decoupling capacitor pin (v refh ) v refh is the power supply for setting the reference voltage. connect the v refh pin to the same voltage potential as v ddad . see section 3. analog-to-digital converter (adc) . 1.4.9 adc voltage reference low pin (v refl ) v refl is the lower reference supply for the adc. connect the v refl pin to the same voltage potential as v ssad . see section 3. analog-to-digital converter (adc) . 1.4.10 port a input/output (i/o) pins (pta7?pta0) pta7?pta0 are general-purpose bidirectional input/output (i/o) port pins. see section 10. input/output (i/o) ports (ports) . 1.4.11 port b i/o pins (ptb7/atd7?ptb0/atd0) port b is an 8-bit special function port that shares all eight pins with the analog-to-digital converter (adc). see section 3. analog-to-digital converter (adc) and section 10. input/output (i/o) ports (ports) . 1.4.12 port c i/o pins (ptc6?ptc2 and ptc1/atd9?ptc0/atd8) ptc6?ptc2 are general-purpose bi directional i/o port pins (see section 10. input/output (i/o) ports (ports) ). ptc1/atd9?ptc0/atd8 are special function port pins that are shared with the analog-to-digital converter (adc). see section 3. analog-to-digital converter (adc) and section 10. input/output (i/o) ports (ports) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 26 general description motorola 1.4.13 port d input-only pins (ptd6/is3 ?ptd4/is1 and ptd3/fault4?ptd0/fault1) ptd6/is3 ?ptd4/is1 are special function input-only port pins that also serve as current sensing pins for the pulse-width modulator module (pwmmc). ptd3/fault4?ptd0/fault1 are special func tion port pins that also serve as fault pins for the pwmmc. see section 12. pulse-width modulator for motor control (pwmmc) and section 10. input/output (i/o) ports (ports) . 1.4.14 pwm pins (pwm6?pwm1) pwm6?pwm1 are dedicated pins used for the outputs of the pulse-width modulator module (pwmmc). these are high-current sink pins. see section 12. pulse-width modulator for motor control (pwmmc) and section 19. electrical specifications . 1.4.15 pwm ground pin (pwmgnd) pwmgnd is the ground pin for the pulse-width modulator module (pwmmc). this dedicated ground pin is used as the ground for the six high-current pwm pins. see section 12. pulse-width modulator for motor control (pwmmc) . 1.4.16 port e i/o pins (pte7/tch3a?pte3/tclka and pte2/tch1b?pte0/tclkb) port e is an 8-bit special function port that shares its pins with the two timer interface modules (tima and timb). see section 16. timer interface a (tima) , section 17. timer interface b (timb) , and section 10. input/output (i/o) ports (ports) . 1.4.17 port f i/o pins (ptf5/txd?ptf4/rxd and ptf3/miso?ptf0/spsck) port f is a 6-bit special function port that shares two of its pins with the serial communications interface module (sci) and four of its pins with the serial peripheral interface module (spi). see section 15. serial peripheral interface module (spi) , section 13. serial communications interface module (sci) , and section 10. input/output (i/o) ports (ports) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 27 data sheet ? mc68hc9 08mr32 mc68HC908MR16 section 2. memory 2.1 introduction the central processor unit (cpu08) can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 32 kbytes of flash 768 bytes of random-access memory (ram) 46 bytes of user-defined vectors 240 bytes of monitor read-only memory (rom) 2.2 unimplemented memory locations some addresses are unimplemented. ac cessing an unimplemented address can cause an illegal address reset. in the memory map and in the input/output (i/o) register summary, unimplemented addresses are shaded. some i/o bits are read only; the write function is unimplemented. writing to a read-only i/o bit has no effect on microcontro ller unit (mcu) operation. in register figures, the write function of read-only bits is shaded. similarly, some i/o bits are write only; the read function is unimplemented. reading of write-only i/o bits has no effect on mc u operation. in register figures, the read function of write-only bits is shaded. 2.3 reserved memory locations some addresses are reserved. writing to a reserved address can have unpredictable effects on mcu operation. in the memory map ( figure 2-1 ) and in the i/o register summary ( figure 2-2 ) reserved addresses are marked with the word reserved. some i/o bits are reserved. writing to a reserved bit can have unpredictable effects on mcu operation. in register figures, reserved bits are marked with the letter r. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 28 memory motorola 2.4 i/o section addresses $0000?$005f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $fe00, sim break status register (sbsr) $fe01, sim reset status register (srsr) $fe03, sim break flag control register (sbfcr) $fe07, flash control register (flcr) $fe0c, break address register high (brkh) $fe0d, break address register low (brkl) $fe0e, break status and control register (brkscr) $fe0f, lvi status and control register (lviscr) $ff7e, flash block protect register (flbpr) $ffff, cop control register (copctl) 2.5 memory map figure 2-1 shows the memory map for the mc68hc908mr32 while the memory map for the mc68HC908MR16 is shown in appendix a. mc68HC908MR16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory memory map mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 29 $0000 $005f i/o registers ? 96 bytes $0060 $035f ram ? 768 bytes $0360 $7fff unimplemented ? 31,904 bytes $8000 $fdff flash ? 32,256 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 reserved $fe05 reserved $fe06 reserved $fe07 reserved $fe08 flash control register (flcr) $fe09 unimplemented $fe0a unimplemented $fe0b unimplemented $fe0c sim break address register high (brkh) $fe0d sim break address register low (brkl) $fe0e sim break flag control register (sbfcr) $fe0f lvi status and control register (lviscr) $fe10 $feff monitor rom ? 240 bytes $ff00 $ff7d unimplemented ? 126 bytes $ff7e flash block protect register (flbpr) $ff7f $ffd1 unimplemented ? 83 bytes $ffd2 $ffff vectors ? 46 bytes figure 2-1. mc68hc908mr32 memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 30 memory motorola addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 113. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 115. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 117. read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r reset: unaffected by reset $0003 port d data register (ptd) see page 119. read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: r r r r r r r r reset: unaffected by reset $0004 data direction register a (ddra) see page 113. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 data direction register b (ddrb) see page 115. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 data direction register c (ddrc) see page 117. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset: 0 0 0 0 0 0 0 0 $0007 unimplemented $0008 port e data register (pte) see page 120. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) see page 122. read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r reset: unaffected by reset $000a unimplemented $000b unimplemented $000c data direction register e (ddre) see page 120. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 0 0 0 0 0 0 0 0 u = unaffected x = indeterminate r = reserved bold = buffered = unimplemented figure 2-2. control, status, and data registers summary (sheet 1 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory memory map mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 31 $000d data direction register f (ddrf) see page 122. read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r reset: 0 0 0 0 0 0 $000e tima status/control register (tasc) see page 245. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $000f tima counter register high (tacnth) see page 247. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0010 tima counter register low (tacntl) see page 247. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0011 tima counter modulo register high (tamodh) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0012 tima counter modulo register low (tamodl) see page 248. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0013 tima channel 0 status/control register (tasc0) see page 249. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0014 tima channel 0 register high (tach0h) see page 252. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0015 tima channel 0 register low (tach0l) see page 252. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0016 tima channel 1 status/control register (tasc1) see page 252. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $0017 tima channel 1 register high (tach1h) see page 252. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0018 tima channel 1 register low (tach1l) see page 252. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered = unimplemented figure 2-2. control, status, and data registers summary (sheet 2 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 32 memory motorola $0019 tima channel 2 status/control register (tasc2) see page 249. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 $001a tima channel 2 register high (tach2h) see page 252. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $001b tima channel 2 register low (tach2l) see page 252. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $001c tima channel 3 status/control register (tasc3) see page 249. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 0 0 0 0 0 0 0 0 $001d tima channel 3 register high (tach3h) see page 252. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $001e tima channel 3 register low (tach3l) see page 252. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $001f configuration register (config) see page 80. read: edge botneg topneg indep lvirst lvipwr stope copd write: reset: 0 0 0 0 1 1 0 0 $0020 pwm control register 1 (pctl1) see page 158. read: disx disy pwmint pwmf isens1 isens0 ldok pwmen write: reset: 0 0 0 0 0 0 0 0 $0021 pwm control register 2 (pctl2) see page 160. read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset: 0 0 0 0 0 0 0 0 $0022 fault control register (fcr) see page 162. read: fint4 fmode4 fint3 fmode3 fint2 fmode2 fint1 fmode1 write: reset: 0 0 0 0 0 0 0 0 $0023 fault status register (fsr) see page 164. read: fpin4 fflag4 fpin3 fflag3 fpin2 fflag2 fpin1 fflag1 write: reset: u 0 u 0 u 0 u 0 $0024 fault acknowledge register (ftack) see page 165. read: 0 0 dt6 dt5 dt4 dt3 dt2 dt1 write: ftack4 ftack3 ftack2 ftack1 reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered = unimplemented figure 2-2. control, status, and data registers summary (sheet 3 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory memory map mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 33 $0025 pwm output control register (pwmout) see page 166. read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset: 0 0 0 0 0 0 0 0 $0026 pwm counter register high (pcnth) see page 156. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0027 pwm counter register low (pcntl) see page 156. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0028 pwm counter modulo register high (pmodh) see page 156. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 x x x x $0029 pwm counter modulo register low (pmodl) see page 156. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: x x x x x x x x $002a pwm 1 value register high (pval1h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002b pwm 1 value register low (pval1l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002c pwm 2 value register high (pval2h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002d pwm 2 value register low (pval2l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002e pwm 3 value register high (pval3h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002f pwm 3 value register low (pval3l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0030 pwm 4 value register high (pval4h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered = unimplemented figure 2-2. control, status, and data registers summary (sheet 4 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 34 memory motorola $0031 pwm 4 value register low (pval4l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0032 pwm 5 value register high (pmval5h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0033 pwm 5 value register low (pval5l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0034 pwm 6 value register high (pval6h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0035 pwm 6 value register low (pmval6l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0036 dead-time write-once register (deadtm) see page 162. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0037 pwm disable mapping write-once register (dismap) see page 149. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0038 sci control register 1 (scc1) see page 183. read: loops ensci txinv m wake ilty pen pty write: reset: 0 0 0 0 0 0 0 0 $0039 sci control register 2 (scc2) see page 185. read: sctie tcie scrie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $003a sci control register 3 (scc3) see page 187. read: r8 t8 00 orie neie feie peie write: r r r reset: u u 0 0 0 0 0 0 $003b sci status register 1 (scs1) see page 188. read: scte tc scrf idle or nf fe pe write: r r r r r r r r reset: 1 1 0 0 0 0 0 0 $003c sci status register 2 (scs2) see page 191. read: 0 0 0 0 0 0 bkf rpf write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered = unimplemented figure 2-2. control, status, and data registers summary (sheet 5 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory memory map mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 35 $003d sci data register (scdr) see page 192. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $003e sci baud rate register (scbr) see page 192. read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: r r r reset: 0 0 0 0 0 0 0 0 $003f irq status/control register (iscr) see page 105. read: 0 0 0 0 irqf 0 imask1 mode1 write: r r r r ack1 reset: 0 0 0 0 0 0 0 0 $0040 adc status and control register (adscr) see page 54. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset: 0 0 0 1 1 1 1 1 $0041 adc data register high right justified mode (adrh) see page 56. read: 0 0 0 0 0 0 ad9 ad8 write: r r r r r r r r reset: unaffected by reset $0042 adc data register low right justified mode (adrl) see page 56. read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: r r r r r r r r reset: unaffected by reset $0043 adc clock register (adclk) see page 57. read: adiv2 adiv1 adiv0 adiclk mode1 mode0 0 0 write: r reset: 0 0 0 0 0 1 0 0 $0044 spi control register (spcr) see page 228. read: sprie r spmstr cpol cpha spwom spe sptie write: reset: 0 0 1 0 1 0 0 0 $0045 spi status and control register (spscr) see page 229. read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset: 0 0 0 0 1 0 0 0 $0046 spi data register (spdr) see page 232. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0047 $0050 unimplemented $0051 timb status/control register (tbsc) see page 265. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered = unimplemented figure 2-2. control, status, and data registers summary (sheet 6 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 36 memory motorola $0052 timb counter register high (tbcnth) see page 267. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0053 timb counter register low (tbcntl) see page 267. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0054 timb counter modulo register high (tbmodh) see page 268. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0055 timb counter modulo register low (tbmodl) see page 268. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0056 timb channel 0 status/control register (tbsc0) see page 269. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0057 timb channel 0 register high (tbch0h) see page 272. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0058 timb channel 0 register low (tbch0l) see page 272. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0059 timb channel 1 status/control register (tbsc1) see page 269. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $005a timb channel 1 register high (tbch1h) see page 272. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $005b timb channel 1 register low (tbch1l) see page 272. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $005c pll control register (pctl) see page 69. read: pllie pllf pllon bcs 1111 write: r r r r r reset: 0 0 1 0 1 1 1 1 $005d pll bandwidth control register (pbwc) see page 71. read: auto lock acq xld 0000 write: r r r r r reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered = unimplemented figure 2-2. control, status, and data registers summary (sheet 7 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory memory map mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 37 $005e pll programming register (ppg) see page 72. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 0 1 1 0 0 1 1 0 $005f unimplemented $fe00 sim break status register (sbsr) see page 207. read: rr r r r rbwr write: reset: 0 $fe01 sim reset status register (srsr) see page 207. read: por pin cop ilop ilad menrst lvi 0 write: r r r r r r r r reset: 1 0 0 0 0 0 0 0 $fe03 sim break flag control register (sbfcr) see page 208. read: bcfe r r r r r r r write: reset: 0 $fe08 flash control register (flcr) see page 41. read: 0 0 0 0 hven mass erase pgm write: reset: 0 0 0 0 0 0 0 0 $fe0c break address register high (brkh) see page 276. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $fe0d break address register low (brkl) see page 276. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $fe0e break status and control register (brkscr) see page 276. read: brke brka 00 0 000 write: reset: 0 0 0 0 0 0 0 0 $fe0f lvi status and control register (lviscr) see page 109. read: lviout 0 trpsel 00000 write: r r r r r r r reset: 0 0 0 0 0 0 0 0 $ff7e flash block protect register (flbpr) see page 45. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: 0 0 0 0 0 0 0 0 $ffff cop control register (copctl) see page 85. read: low byte of reset vector write: clear cop counter reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 u = unaffected x = indeterminate r = reserved bold = buffered = unimplemented figure 2-2. control, status, and data registers summary (sheet 8 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 38 memory motorola table 2-1 is a list of vector locations. table 2-1. vector addresses address vector low $ffd2 sci transmit vector (high) $ffd3 sci transmit vector (low) $ffd4 sci receive vector (high) $ffd5 sci receive vector (low) $ffd6 sci error vector (high) $ffd7 sci error vector (low) $ffd8 spi transmit vector (high) (1) $ffd9 spi transmit vector (low) (1) $ffda spi receive vector (high) (1) $ffdb spi receive vector (low) (1) $ffdc a/d vector (high) $ffdd a/d vector (low) $ffde timb overflow vector (high) $ffdf timb overflow vector (low) $ffe0 timb channel 1 vector (high) $ffe1 timb channel 1 vector (low) $ffe2 timb channel 0 vector (high) $ffe3 timb channel 0 vector (low) $ffe4 tima overflow vector (high) $ffe5 tima overflow vector (low) $ffe6 tima channel 3 vector (high) $ffe7 tima channel 3 vector (low) $ffe8 tima channel 2 vector (high) $ffe9 tima channel 2 vector (low) $ffea tima channel 1 vector (high) $ffeb tima channel 1 vector (low) $ffec tima channel 0 vector (high) $ffed tima channel 0 vector (low) 1. the spi module is not available in the 56-pin sdip package. priority f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory monitor rom mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 39 2.6 monitor rom the 240 bytes at addresses $fe10?$feff are reserved rom addresses that contain the instructions for the monitor functions. see 18.3 monitor rom (mon) . 2.7 random-access memory (ram) addresses $0060?$035f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer al lows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. $ffee pwmmc vector (high) $ffef pwmmc vector (low) $fff0 fault 4 (high) $fff1 fault 4 (low) $fff2 fault 3 (high) $fff3 fault 3 (low) $fff4 fault 2 (high) $fff5 fault 2 (low) $fff6 fault 1 (high) $fff7 fault 1 (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector (high) $fffd swi vector (low) high $fffe reset vector (high) $ffff reset vector (low) table 2-1. vector addresses (continued) address vector priority f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 40 memory motorola within page zero are 160 bytes of ram. because the location of the stack ram is programmable, all page zero ram locati ons can be used for input/output (i/o) control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access efficiently all page zero ram locations. page zero ram, t herefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the central pr ocessor unit (cpu) uses five bytes of the stack to save the contents of the cpu registers. note: for m68hc05 and m1468hc05 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines . the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.8 flash memory (flash) the flash memory is an array of 32,256 bytes with an additional 46 bytes of user vectors and one byte of block protection. note: an erased bit reads as a 1 and a programmed bit reads as a 0. program and erase operations are facilit ated through control bits in a memory mapped register. details for these operations appear later in this section. memory in the flash array is organized into two rows per page. the page size is 128 bytes per page. the minimum erase page size is 128 bytes. programming is performed on a row basis, 64 bytes at a time. the address ranges for the user memory and vectors are: $8000?$fdff, user memory $ff7e, block protect register (flbpr) $fe08, flash control register (flcr) $ffd2?$ffff, reserved for user-defined interrupt and reset vectors programming tools are available from motorola. contact a local motorola representative for more information. note: a security feature prevents viewing of the flash contents. (1) 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory flash memory (flash) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 41 2.8.1 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the 32-kbyte flash array for mass erase operation. mass erase is disabled if any flash block is protected 1 = mass erase operation selected 0 = mass erase operation unselected erase ? erase control bit this read/write bit configures the memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for program operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-3. flash control register (flcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 42 memory motorola 2.8.2 flash page erase operation use this step-by-step procedure to erase a page (128 bytes) of flash memory. 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for a time, t nvh (minimum 5 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. in applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specification. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specif ication to get a shorter cycle time. 2.8.3 flash mass erase operation use this step-by-step procedure to erase the entire flash memory. 1. set both the erase bit and the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t merase (minimum 4 ms). 7. clear the erase and mass bits. note: mass erase is disabled whene ver any block is protected (flbpr does not equal $ff). 1. when in monitor mode, with security sequence failed (see 18.3.2 security ), write to the flash block protect register instead of any flash address. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory flash memory (flash) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 43 8. wait for a time, t nvhl (minimum 100 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. 2.8.4 flash program operation use the following step-by-step procedure to program a row of flash memory. figure 2-4 shows a flowchart of the programming algorithm. note: only bytes which are currently $ff may be programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read the flash block protect register. 3. write any data to any flash location within the address range desired. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t pgs (minimum 5 s). 7. write data to the flash address being programmed (1) . 8. wait for time, t prog (minimum 30 s). 9. repeat step 7 and 8 until all desired bytes within the row are programmed. 10. clear the pgm bit (1) . 11. wait for time, t nvh (minimum 5 s). 12. clear the hven bit. 13. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note: the cop register at location $ffff sh ould not be written between steps 5-12, when the hven bit is set. since this regi ster is located at a valid flash address, unpredictable behavior may occur if this location is written while hven is set. this program sequence is repeated throughout the memory until all data is programmed. note: programming and erasing of flash locati ons cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum, see 19.6 flash memory characteristics . 1. the time between each flash address change, or the time between the last flash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 44 memory motorola figure 2-4. flash programming flowchart set hven bit read the flash block protect register write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? yes no end of programming the time between each flash address change (step 7 to step 7), or must not exceed th e maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) note: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory flash memory (flash) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola memory 45 2.8.5 flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provis ion is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. this protection is done by using a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff ). when the memory is protected, the hven bit cannot be set in either erase or program operations. note: in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit when the flbpr is programmed with all 0s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1s), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory, whose address ranges are shown in 2.8.6 flash block protect register . once the flbpr is programmed with a value other than $ff, any erase or program of the flbpr or the protected block of flash memory is prohibited. mass erase is disabled whenever any block is protec ted (flbpr does not equal $ff). the flbpr itself can be erased or program med only with an external voltage, v tst , present on the irq pin. this voltage also allows entry from reset into the monitor mode. 2.8.6 flash block protect register the flash block protect register (flbpr) is implemented as a byte within the flash memory, and therefore can be written only during a programming sequence of the flash memory. the value in this register determines the starting location of the protected range within the flash memory. bpr[7:0] ? flash block protect bits these eight bits represent bits [14:7] of a 16-bit memory address. bit 15 is 1 and bits [6:0] are 0s. address: $ff7e bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 u = unaffected by reset. initial value from factory is 1. write to this register by a programming sequence to the flash memory. figure 2-5. flash block protect register (flbpr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 46 memory motorola the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this start address to the end of flash memory at $ffff. with this mechanism, the protect start address can be xx00 and xx80 (128 bytes page boundaries) within the flash memory. figure 2-6. flash block protect start address refer to table 2-2 for examples of the protect start address. 2.8.7 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the wait instruction should not be execut ed while performing a program or erase operation on the flash. otherwise, the operation will discontinue, and the flash will be on standby mode. 2.8.8 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash, otherwise the operation will discontinue, and the flash will be on standby mode note: standby mode is the power-saving mode of the flash module in which all internal control signals to the flash are inacti ve and the current consumption of the flash is at a minimum. table 2-2. examples of protect start address bpr[7:0] start of address of protect range $00 the entire flash memory is protected. $01 ( 0000 0001 ) $8080 (1 000 0000 1 000 0000) $02 ( 0000 0010 ) $8100 (1 000 0001 0 000 0000) and so on... $fe ( 1111 1110 ) $ff00 (1 111 1111 0 000 0000) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff. 1 flbpr value 16-bit memory address 0000000 start address of flash block protect f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola analog-to-digital converter (adc) 47 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 3. analog-to-digital converter (adc) 3.1 introduction this section describes the 10-bit analog-to-digital converter (adc). 3.2 features features of the adc module include: 10 channels with multiplexed input linear successive approximation 10-bit resolution, 8-bit accuracy single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock left or right justified result left justified sign data mode high impedance buffered adc input 3.3 functional description ten adc channels are available for sa mpling external sources at pins ptc1/atd9:ptc0/atd8 and ptb7/atd7:ptb0/atd0. to achieve the best possible accuracy, these pins are impl emented as input-only pins when the analog-to-digital (a/d) feature is enabled. an analog multiplexer allows the single adc to select one of the 10 adc channels as adc voltage in (adcvin). adcvin is converted by the successive approxi mation algorithm. when the conversion is completed, the adc places the result in the adc data register (adrh and adrl) and sets a flag or generates an interrupt. see figure 3-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 48 analog-to-digital converter (adc) motorola analog-to-digital converter (adc) figure 3-1. block diagram highlighting adc block and pins clock generator module system integration module serial communications interface module serial peripheral interface module (2) timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 112 bytes user flash ? 32,256 bytes user ram ? 768 bytes monitor rom ? 240 bytes user flash vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq v ss v dd v ddad pta7?pta0 pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b (1) pte1/tch0b (1) pte0/tclkb (1 ) ptf5/txd ptf4/rxd ptf3/miso (1) ptf2/mosi (1) ptf1/ss (1) ptf0/spsck (1) timer interface module b pulse-width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9 (1) ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssad v dda v ssa (3) pwmgnd v refl (3) v refh notes: 1. these pins are not available in the 56-pin sdip package. 2. this module is not avail able in the 56-pin sdip package. 3. in the 56-pin sdip package, these pins are bonded together. single break module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola analog-to-digital converter (adc) 49 figure 3-2. adc block diagram 3.3.1 adc port i/o pins ptc1/atd9:ptc0/atd8 and ptb7/atd7:ptb0/atd0 are general-purpose i/o pins that are shared with the adc channels. the channel select bits define which adc c hannel/port pin will be used as the input signal. the adc overrides the port logic when that port is selected by the adc multiplexer. the remaining adc channels/port pins are controlled by the port logic and can be used as general-purpose input/output (i/o) pins. writes to the port register or ddr will not have any effect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a 0. 3.3.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $3ff (full scale). if the input voltage equals v refl , the adc converts it to $000. input voltages between v refh and v refl are straight-line linear conversions. all other input voltages will result in $3ff if greater than v refh and $000 if less than v refl . note: input voltage should not exceed the analog supply voltages. see 19.13 analog-to-digital converter (adc) characteristics . read ptb/ptc ptb/cx interrupt logic channel select adc clock generator conversion complete adc voltage in advin adc clock cgmxclk bus clock adch[4:0] adc data registers adiv[2:0] adiclk aien coco disable adc channel x internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 50 analog-to-digital converter (adc) motorola 3.3.3 conversion time conversion starts after a write to the ad scr. a conversion is between 16 and 17 adc clock cycles, therefore: the adc conversion time is determined by the clock source chosen and the divide ratio selected. the clock source is either the bus clock or cgmxclk and is selectable by adiclk located in the adc clock register. for example, if cgmxclk is 4 mhz and is selected as the adc input clock source, the adc input clock divide-by-4 prescale is selected and the cpu bus frequency is 8 mhz: note: the adc frequency must be between f adic minimum and f adic maximum to meet a/d specifications. see 19.13 analog-to-digital converter (adc) characteristics . since an adc cycle may be comprised of se veral bus cycles (eight, 136 minus 128, in the previous example) and the start of a conversion is initia ted by a bus cycle write to the adscr, from zero to eight additional bus cycles may occur before the start of the initial adc cycle. this re sults in a fractional adc cycle and is represented as the 17th cycle. 3.3.4 continuous conversion in continuous conversion mode, the adc data registers adrh and adrl will be filled with new data after each conversion. data from the previous conversion will be overwritten whether that data has b een read or not. conv ersions will continue until the adco bit is cleared. the coco bit is set after each conversion and will stay set until the next read of the adc data register. when a conversion is in process and the adsc r is written, the current conversion data should be discarded to prevent an incorrect reading. 3.3.5 result justification the conversion result may be formatted in four different ways: 1. left justified 2. right justified 3. left justified sign data mode 4. 8-bit truncation mode 16 to17 adc cycles conversion time = adc frequency number of bus cycles = conv ersion time x cpu bus frequency 16 to 17 adc cycles conversion time = 4 mhz/4 number of bus cycles = 16 s x 8 mhz = 128 to 136 cycles = 16 to 17 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola analog-to-digital converter (adc) 51 all four of these modes are controlled using mode0 and mode1 bits located in the adc clock register (adcr). left justification will place the eight most significant bits (msb) in the corresponding adc data register high, adrh. this may be useful if the result is to be treated as an 8-bit result where the two least significant bits (lsb), located in the adc data register low, adrl, can be ignored. however, adrl must be read after adrh or else the interlocking will prevent a ll new conversions from being stored. right justification will place only the two msbs in the corresponding adc data register high, adrh, and the eight lsbs in adc data register low, adrl. this mode of operation typically is used when a 10-bit unsigned result is desired. left justified sign data mode is similar to le ft justified mode with one exception. the msb of the 10-bit result, ad9 located in adrh, is complemented. this mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. finally, 8-bit trun cation mode will place the eight msbs in adc data register low, adrl. the two lsbs are dropped. this mode of operation is used when compatibility wi th 8-bit adc designs are required. no interlocking between adrh and adrl is present. note: quantization error is affected when only the most significant eight bits are used as a result. see figure 3-3 . figure 3-3. 8-bit truncation mode error ideal 10-bit characteristic with quantization = 1/2 ideal 8-bit characteristic with quantization = 1/2 10-bit truncated to 8-bit result when truncation is used, error from ideal 8-bit = 3/8 lsb due to non-ideal quantization. 000 001 002 003 004 005 006 007 008 009 00a 00b 000 001 002 003 8-bit resul t 10-bit result input voltage represented as 10-bit input voltage represented as 8-bit 1/2 2 1/2 4 1/2 6 1/2 8 1/2 1 1/2 3 1/2 5 1/2 7 1/2 9 1/2 1/2 2 1/2 1 1/2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 52 analog-to-digital converter (adc) motorola 3.3.6 monotonicity the conversion process is monotonic and has no missing codes. 3.4 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 3.5 wait mode the wait instruction can put the mcu in low power-consumption standby mode. the adc continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting adch[4:0] in the adc status and control register before executing the wait instruction. 3.6 i/o signals the adc module has 10 input signals that are shared with port b and port c. 3.6.1 adc analog power pin (v ddad ) the adc analog portion uses v ddad as its power pin. connect the v ddad pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddad for good results. note: route v ddad carefully for maximum noise imm unity and place bypass capacitors as close as possible to the package. 3.6.2 adc analog ground pin (v ssad ) the adc analog portion uses v ssad as its ground pin. connect the v ssad pin to the same voltage potential as v ss . 3.6.3 adc voltage reference pin (v refh ) v refh is the power supply for setting the reference voltage v refh . connect the v refh pin to the same voltage potential as v ddad . there will be a finite current associated with v refh . see section 19. electrical specifications . note: route v refh carefully for maximum noise imm unity and place bypass capacitors as close as possible to the package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o signals mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola analog-to-digital converter (adc) 53 3.6.4 adc voltage reference low pin (v refl ) v refl is the lower reference supply for the adc. connect the v refl pin to the same voltage potential as v ssad . a finite current will be associated with v refl . see section 19. electrical specifications . note: in the 56-pin shrink dual in-line package (sdip), v refl and v ssad are tied together. 3.6.5 adc voltage in (advin) advin is the input voltage signal from one of the 10 adc channels to the adc module. 3.6.6 adc external connections this section describes the adc external connections: v refh and v refl , anx, and grounding. 3.6.6.1 v refh and v refl both ac and dc current are drawn through the v refh and v refl loop. the ac current is in the form of current spikes required to supply charge to the capacitor array at each successive approximation step. the current flows through the internal resistor string. the best exter nal component to meet both these current demands is a capacitor in the 0.01 f to 1 f range with good high frequency characteristics. this capacitor is connected between v refh and v refl and must be placed as close as possible to the pac kage pins. resistance in the path is not recommended because the dc current will cause a voltage drop which could result in conversion errors. 3.6.6.2 anx empirical data shows that capacitors from the analog inputs to v refl improve adc performance. 0.01- f and 0.1- f capacitors with good high-frequency characteristics are sufficient. these capacit ors must be placed as close as possible to the package pins. 3.6.6.3 grounding in cases where separate power supplies ar e used for analog and digital power, the ground connection between these supplies should be at the v ssad pin. this should be the only ground connection between these supplies if possible. the v ssa pin makes a good single point ground location. connect the v refl pin to the same potential as v ssad at the single point ground location. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 54 analog-to-digital converter (adc) motorola 3.7 i/o registers these i/o registers control and monitor operation of the adc: adc status and control register, adscr adc data registers, adrh and ardl adc clock register, adclk 3.7.1 adc status and control register this section describes the function of the adc status and control register (adscr). writing adscr aborts the current conversion and initiates a new conversion. coco ? conversions complete bit in non-interrupt mode (aien = 0), coco is a read-only bit that is set at the end of each conversion. coco will stay set until cleared by a read of the adc data register. reset clears this bit. in interrupt mode (aien = 1), coco is a read-only bit that is not set at the end of a conversion. it always reads as a 0. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupt enabled (aien = 1) note: the write function of the coco bit is reserved. when writing to the adscr register, always have a 0 in the coco bit position. aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion address: $0040 bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00011111 r= reserved figure 3-4. adc status and control register (adscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola analog-to-digital converter (adc) 55 adch[4:0] ? adc channel select bits adch4, adch3, adch2, adch1, and adch0 form a 5-bit field which is used to select one of 10 adc channels. the adc channels are detailed in table 3-1 . note: take care to prevent switching noise from corrupting the analog signal when simultaneously using a port pin as both an analog and digital input. the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not used. note: recovery from the disabled state requires one conversion cycle to stabilize. the voltage levels supplied from internal reference nodes as specified in table 3-1 are used to verify the operation of the adc both in production test and for user applications. table 3-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 ptc0/atd8 01001 ptc1/atd9 (1) 1. atd9 is not available in the 56-pin sdip package. 01010 unused (2) 01011 ? 01100 ? 01101 ? 01110 ? 01111 ? 10000 ? 11010 unused (2) 2. used for factory testing. 11011 reserved (3) 3. if any unused channels are selected, the resulting adc conversion will be unknown. 1 1 1 0 0 unused (2) 1 1 1 0 1 v refh 1 1 1 1 0 v refl 1 1 1 1 1 adc power off f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 56 analog-to-digital converter (adc) motorola 3.7.2 adc data register high in left justified mode, this 8-bit result re gister holds the eight msbs of the 10-bit result. this register is updated eac h time an adc single channel conversion completes. reading adrh latches the conten ts of adrl until adrl is read. until adrl is read, all subsequent adc results will be lost. in right justified mode, this 8-bit result register holds the two msbs of the 10-bit result. all other bits read as 0. this regi ster is updated each time a single channel adc conversion completes. reading adrh latches the contents of adrl until adrl is read. until adrl is read, all subsequent adc results will be lost. 3.7.3 adc data register low in left justified mode, this 8-bit result register holds the two lsbs of the 10-bit result. all other bits read as 0. this register is updated each time a single channel adc conversion completes. reading adrh latches the contents of adrl until adrl is read. until adrl is read, all subsequent adc results will be lost. address: $0041 bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset: unaffected by reset r= reserved figure 3-5. adc data register high (adrh) left justified mode address: $0041 bit 7654321bit 0 read:000000ad9ad8 write:rrrrrrrr reset: unaffected by reset r= reserved figure 3-6. adc data register high (adrh) right justified mode address: $0042 bit 7654321bit 0 read:ad1ad0000000 write:rrrrrrrr reset: unaffected by reset r= reserved figure 3-7. adc data register low (adrl) left justified mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola analog-to-digital converter (adc) 57 in right justified mode, this 8-bit result register holds the eight lsbs of the 10-bit result. this register is updated each time an adc conversion completes. reading adrh latches the contents of adrl until adrl is read. until adrl is read, all subsequent adc results will be lost. in 8-bit mode, this 8-bit result register holds the eight msbs of the 10-bit result. this register is updated each time an adc conv ersion completes. in 8-bit mode, this register contains no interlocking with adrh. 3.7.4 adc clock register this register selects the clock frequency for the adc, selecting between modes of operation. adiv2:adiv0 ? adc clock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit fi eld which selects the divide ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurations. address: $0042 bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrrrrrrr reset: unaffected by reset r= reserved figure 3-8. adc data register low (adrl) right justified mode address: $0042 bit 7654321bit 0 read: ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 write:rrrrrrrr reset: unaffected by reset r= reserved figure 3-9. adc data register low (adrl) 8-bit mode address: $0043 bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk mode1 mode0 0 0 write: r reset:00000100 r= reserved figure 3-10. adc clock register (adclk) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 58 analog-to-digital converter (adc) motorola adiclk ? adc input clock select bit adiclk selects either bus clock or cg mxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or greater than 1 mhz, cgmxclk can be used as the clock source for t he adc. if cgmxclk is less than 1 mhz, use the pll-generated bus clock as the cl ock source. as long as the internal adc clock is at f adic , correct operation can be guaranteed. see 19.13 analog-to-digital converter (adc) characteristics . 1 = internal bus clock 0 = external clock, cgmxclk mode1:mode0 ? modes of result justification bits mode1:mode0 selects among four modes of operation. the manner in which the adc conversion results will be placed in the adc data registers is controlled by these modes of operation. re set returns right-justified mode. 00 = 8-bit truncation mode 01 = right justified mode 10 = left justified mode 11 = left justified sign data mode table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care cgmxclk or bus frequency f adic = adiv[2:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 59 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 4. clock generator module (cgm) 4.1 introduction this section describes the clock generator module (cgm, version a). the cgm generates the crystal clock signal, cgmxcl k, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system integration module (s im) derives the system clocks. cgmout is based on either the crystal cl ock divided by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a frequency generator designed for use with crystals or ceramic resonators. the pll can generate an 8-mhz bus frequency without us ing a 32-mhz external clock. 4.2 features features of the cgm include: pll with output frequency in integer multiples of the crystal reference programmable hardware voltage-controlled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitter operation automatic frequency lock detector central processor unit (cpu) interrupt on entry or exit from locked condition 4.3 functional description the cgm consists of three major submodules: 1. crystal oscillator circuit ? the cr ystal oscillator circuit generates the constant crystal frequency clock, cgmxclk. 2. phase-locked loop (pll) ? the pll generates the programmable vco frequency clock, cgmvclk. 3. base clock selector circuit ? this so ftware-controlled circuit selects either cgmxclk divided by two or the vco cl ock, cgmvclk, divided by two as the base clock, cgmout. the sim derives the system clocks from cgmout. figure 4-1 shows the structure of the cgm. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 60 clock generator module (cgm) motorola figure 4-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] cgmxfc v ss v dda osc1 osc2 to sim to sim ptc2 monitor mode a b s* user mode *when s = 1, cgmout = b addr. register name bit 7654321bit 0 $005c pll control register (pctl) see page 69. read: pllie pllf pllon bcs 1111 write: r r r r r reset:00101111 $005d pll bandwidth control register (pbwc) see page 71. read: auto lock acq xld 0000 write: r r r r r reset:00000000 $005e pll programming register (ppg) see page 72. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 r=reserved figure 4-2. cgm i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 61 4.3.1 crystal oscillator circuit the crystal oscillator circuit consists of an inverting amplifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the output. the simoscen signal from the system integration module (sim) enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to produce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50 percent and depends on external factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal oscillator circuit. connect the external clock to th e osc1 pin and let the osc2 pin float. 4.3.2 phase-locked loop circuit (pll) the pll is a frequency generator that c an operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. 4.3.2.1 pll circuits the pll consists of these circuits: voltage-controlled oscillator (vco) modulo vco frequency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external no ise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency within this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , (4.9152 mhz) times a linear factor, l or (l) f nom . cgmrclk is the pll reference clock, a buffered version of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to the pll through a buffer. the buffer output is the final reference clock, cgmrdv, running at a frequency, f rdv =f rclk . the vco?s output clock, cgmvclk, running at a frequency, f vclk , is fed back through a programmable modulo divider. the modulo divider reduces the vco f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 62 clock generator module (cgm) motorola clock by a factor, n. the divider?s out put is the vco feedback clock, cgmvdv, running at a frequency, f vdv =f vclk/n . (see 4.3.2.4 programming the pll for more information.) the phase detector then compares the vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor connect ed to cgmxfc based on the width and direction of the correction pulse. the filter can make fast or slow corrections depending on its mode, described in 4.3.2.2 acquisition and tracking modes . the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequenc ies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency, f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. 4.3.2.2 acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: 1. acquisition mode ? in acquisition mode, the filter can make large frequency corrections to the vco. this mode is used at pll startup or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. see 4.5.2 pll bandwidth control register . 2. tracking mode ? in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. see 4.3.3 base clock selector circuit . the pll is automatically in tracking mode when not in acquisition mode or when the acq bit is set. 4.3.2.3 manual and automatic pll bandwidth modes the pll can change the bandwidth or operati onal mode of the loop filter manually or automatically. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth control mode also is used to determine when the vc o clock, cgmvclk, is safe to use as the source for the base clock, cgmout. see 4.5.2 pll bandwidth control register . if pll interrupts are enabled, the software can wait for a pll interrupt request and then check the lock bit. if interrupts are disabled, software can poll the lock bit continuously (during pll start up, usually) or at periodic intervals. in either case, when the lock bit is set, t he vco clock is safe to use as the source f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 63 for the base clock. see 4.3.3 base clock selector circuit . if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. see 4.6 interrupts for information and precautions on using interrupts. these conditions apply when the pll is in automatic bandwidth control mode: the acq bit (see 4.5.2 pll bandwidth control register ) is a read-only indicator of the mode of the filter. for more information, see 4.3.2.2 acquisition and tracking modes . the acq bit is set when the vco frequency is within a certain tolerance, ? trk , and is cleared when the vco frequency is out of a certain tolerance, ? unt . for more information, see 4.8 acquisition/lock time specifications . the lock bit is a read-only indicator of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance, ? unl . for more information, see 4.8 acquisition/lock time specifications . cpu interrupts can occur if enabled (pllie = 1) when the pll?s lock condition changes, toggling the lock bit. for more information, see 4.5.1 pll control register . the pll also may operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax and require fast startup. these conditions apply when in manual mode: acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 4.8 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control register (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 64 clock generator module (cgm) motorola 4.3.2.4 programming the pll use this 9-step procedure to program the pll. table 4-1 lists the variables used and their meaning. 1. choose the desired bus frequency, f busdes . example: f busdes = 8 mhz 2. calculate the desired vco frequency, f vclkdes . f vclkdes = 4 x f busdes example: f vclkdes = 4 x 8 mhz = 32 mhz 3. using a reference frequency, f rclk , equal to the crystal frequency, calculate the vco frequency multiplier, n. round the result to the nearest integer. 4. calculate the vco frequency, f vclk . 5. calculate the bus frequency, f bus , and compare f bus with f busdes . 6. if the calculated f bus is not within the tolerance limits of the application, select another f busdes or another f rclk . table 4-1. variable definitions variable definition f busdes desired bus clock frequency f vclkdes desired vco clock frequency f rclk chosen reference crystal frequency f vclk calculated vco clock frequency f bus calculated bus clock frequency f nom nominal vco center frequency f vrs shifted fco center frequency f vclkdes f rclk n = example: n = 32 mhz 4 mhz = 8 mhz f vclk = n x f rclk example: f vclk = 8 x 4 mhz = 32 mhz f bus = f vclk 4 example: n = 32 mhz 4 mhz = 8 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 65 7. using the value 4.9152 mhz for f nom , calculate the vco linear range multiplier, l. the linear range multiplier controls the frequency range of the pll. 8. calculate the vco center-of-range frequency, f vrs . the center-or-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. f vrs = l x f nom example: f vrs = 7 x 4.9152 mhz = 34.4 mhz for proper operation, caution: exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. 9. program the pll registers accordingly: a. in the upper four bits of the pll programming register (ppg), program the binary equivalent of n. b. in the lower four bits of the pll programming register (ppg), program the binary equivalent of l. 4.3.2.5 special programming exceptions the programming method described in 4.3.2.4 programming the pll does not account for possible exceptions. a value of 0 for n or l is meaningless when used in the equations given. to account for these exceptions: a 0 value for n is interpreted exactly the same as a value of 1. a 0 value for l disables the pll and prevents its selection as the source for the base clock. see 4.3.3 base clock selector circuit . 4.3.3 base clock selector circuit this circuit is used to select either the crystal clock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input clocks go through a transition control circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the output of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus clock frequency, which example: l = 32 mhz 4.9152 mhz = 7 mhz l = round f vclk f nom ( ) f vrs ? f vclk | f nom 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 66 clock generator module (cgm) motorola is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crystal clock would be forced as the source of the base clock. 4.3.4 cgm external connections in its typical configuration, the cgm requires seven external components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 4-3 . figure 4-3 shows only the logical representation of the internal components and may not represent actual circuitry. figure 4-3. cgm external connections the oscillator configuration uses five components: 1. crystal, x 1 2. fixed capacitor, c 1 3. tuning capacitor, c 2 (can also be a fixed capacitor) 4. feedback resistor, r b 5. series resistor, r s (optional) c1 c2 c f simoscen cgmxclk r b x1 r s * c byp osc1 osc2 v ss cgmxfc v dda v dd *rs can be 0 (shorted) when used with higher frequency crystals. refer to manufacturer?s data. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) i/o signals mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 67 the series resistor (r s ) is included in the diagram to fo llow strict pierce oscillator guidelines and may not be required for a ll ranges of operation, especially with high-frequency crystals. refer to the cr ystal manufacturer?s data for more information. figure 4-3 also shows the external components for the pll: bypass capacitor, c byp filter capacitor, c f note: routing should be done with great care to minimize signal cross talk and noise. (see 4.8 acquisition/lock time specifications for routing information and more information on the filter capacitor?s value and its effects on pll performance.) 4.4 i/o signals this section describes the cgm input/output (i/o) signals. 4.4.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 4.4.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the cr ystal oscillator inverting amplifier. 4.4.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. a small external capacitor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the c f connection. 4.4.4 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. connect the v dda pin to the same voltage potential as the v dd pin. note: route v dda carefully for maximum noise imm unity and place bypass capacitors as close as possible to the package. 4.4.5 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables the oscillator and pll. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 68 clock generator module (cgm) motorola 4.4.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 4-3 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the dut y cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at startup. 4.4.7 cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50 percent duty cycle clock running at twice the bus frequency. cgmout is softw are programmable to be either the oscillator output, cgmxclk, divided by tw o or the vco clock, cgmvclk, divided by two. 4.4.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 4.5 cgm registers these registers control and monitor operation of the cgm: pll control register (pctl) ? see 4.5.1 pll control register pll bandwidth control register (pbwc) ? see 4.5.2 pll bandwidth control register pll programming register (ppg) ? see 4.5.3 pll programming register figure 4-4 is a summary of the cgm registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 69 4.5.1 pll control register the pll control register (pctl) contai ns the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. pllie ? pll interrupt enable bit this read/write bit enables the pll to generate an interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag this read-only bit is set whenever the lock bit toggles. pllf generates an interrupt request if the pllie bit also is set. pllf always reads as logic 0 when addr. register name bit 7654321bit 0 $005c pll control register (pctl) see page 69. read: pllie pllf pllon bcs 1111 write: r r r r r reset:00101111 $005d pll bandwidth control register (pbwc) see page 71. read: auto lock acq xld 0000 write: r r r r r reset:00000000 $005e pll programming register (ppg) see page 72. read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 r = reserved notes: 1. when auto = 0, pllie is forced to logic 0 and is read-only. 2. when auto = 0, pllf and lock read as logic 0. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs[ 7:4] = $0, bcs is forced to logic 0 and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 4-4. cgm i/o register summary address: $005c bit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: r rrrr reset:00101111 r = reserved figure 4-5. pll control register (pctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 70 clock generator module (cgm) motorola the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently clear the pllf bit. an y read or read-modify-write operation on the pll control register clears the pllf bit. pllon ? pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco cloc k is driving the base clock, cgmout (bcs = 1). see 4.3.3 base clock selector circuit . reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output, cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmvclk cycles to complete the transition from one source clock to the other. during the trans ition, cgmout is held in stasis. see 4.3.3 base clock selector circuit . reset clears the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note: pllon and bcs have built-in protection that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. see 4.3.3 base clock selector circuit . pctl[3:0] ? unimplemented bits these bits provide no function and always read as logic 1s. 4.5.2 pll bandwidth control register the pll bandwidth control register (pbwc): selects automatic or manual (softwar e-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode, indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 71 auto ? automatic ba ndwidth control bit this read/write bit selects automatic or manual bandwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mo de. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (aut o = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ? crystal loss detect bit when the vco output, cgmvclk, is driv ing cgmout, this read/write bit can indicate whether the crystal reference frequency is active or not. to check the status of the crystal reference, follow these steps: 1. write a logic 1 to xld. 2. wait n 4 cycles. (n is the vco frequency multiplier.) 3. read xld. the crystal loss detect function works only when the bcs bit is set, selecting cgmvclk to drive cgmout. when bcs is clear, xld always reads as logic 0. 1 = crystal reference is not active. 0 = crystal reference is active. pbwc[3:0] ? reserved for test these bits enable test functions not avai lable in user mode. to ensure software portability from development systems to user applications, software should write 0s to pbwc[3:0] whenever writing to pbwc. address: $005d bit 7654321bit 0 read: auto lock acq xld 0000 write: r rrrr reset:00000000 r = reserved figure 4-6. pll bandwidth control register (pbwc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 72 clock generator module (cgm) motorola 4.5.3 pll programming register the pll programming register (ppg) contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the vco. mul[7:4] ? multiplier select bits these read/write bits control the modulo feedback divider that selects the vco frequency multiplier, n. see 4.3.2.1 pll circuits and 4.3.2.4 programming the pll . a value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. reset initializes these bits to $6 to give a default multiply value of 6. note: the multiplier select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1). vrs[7:4] ? vco range select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware center-of-range frequency f vrs . see 4.3.2.1 pll circuits , 4.3.2.4 programming the pll and 4.5.1 pll control register . vrs[7:4] cannot be written when the pllon bit in the pll control register address: $005e bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 4-7. pll programming register (ppg) table 4-2. vco frequency multiplier (n) selection mul7:mul6:mul5:mul4 vco fr equency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) interrupts mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 73 (pctl) is set. see 4.3.2.5 special programming exceptions . a value of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. see 4.3.3 base clock selector circuit and 4.3.2.5 special programming exceptions for more information. reset initializes the bits to $6 to give a default range multiply value of 6. note: the vco range select bits have built-in prot ection that prevents them from being written when the pll is on (pllon = 1) and prevents selection of the vco clock as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be pr ogrammed correctly. incorrect programming may result in failure of the pll to achieve lock. 4.6 interrupts when the auto bit is set in the pll band width control register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts are enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabled and pllf reads as logic 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not frequency-sensitive, in terrupts should be disabled to prevent pll interrupt service routines from impeding so ftware performance or from exceeding stack limitations. note: software can select the cgmvclk divided by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 4.7 wait mode the wait instruction puts the mcu in low power-consumption standby mode. the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselec t the pll output without turning off the pll. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 74 clock generator module (cgm) motorola 4.8 acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensures the highest stability and lowest acquisition/lock times. 4.8.1 acquisition/lock time definitions typical control systems refer to the acquisi tion time or lock time as the reaction time, within specified toler ances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5 percent acquisition time tolerance. if a command instructs the system to change fr om 0 hz to 1 mhz, the acquisition time is the time taken for the frequency to reach 1 mhz 50 khz. fifty khz = 5% of the 1-mhz step input. if the system is operati ng at 1 mhz and suffers a ?100-khz noise hit, the acquisition time is the time ta ken to return from 900 khz to 1 mhz 5khz. five khz = 5% of the 100-khz step input. other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisiti on or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definit ion because the system requires the output frequency to be within a certain toler ance of the desired frequency regardless of the size of the initial error. the discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical pll. therefore, t he definitions for acquisition and lock times for this module are: acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, ? trk . acquisition time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100 percent. in automatic bandwidth control mode (see 4.3.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). lock time, t lock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, ? lock . lock time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100 percent. in automatic bandwidth control mode, lock time ex pires when the lock bit becomes set in the pll bandwidth control register (pbwc). see 4.3.2.3 manual and automatic pll bandwidth modes . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 75 obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 4.8.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user co ntrol via the choice of crystal frequency, f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. see 4.8.3 choosing a filter capacitor . also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it causes small frequency errors which continually c hange the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limi ts. external factors, however, can cause drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacitor filter, capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 4.8.3 choosing a filter capacitor as described in 4.8.2 parametric influences on reaction time , the external filter capacitor, c f , is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. the value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 76 clock generator module (cgm) motorola for proper operation, the external filter capacitor must be chosen according to this equation: for acceptable values of c fact , see 4.8 acquisition/lock time specifications . for the value of v dda , choose the voltage potential at which the mcu is operating. if the power supply is variable, choose a value near the middle of the range of possible supply values. this equation does not always yield a comm only available capac itor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing t he lower size may seem attractive for acquisition time improvement, but the pl l can become unstable. also, always choose a capacitor with a tight tolerance ( 20 percent or better) and low dissipation. 4.8.4 reaction time calculation the actual acquisition and lock times ca n be calculated using the equations here. these equations yield nominal values under these conditions: correct selection of filter capacitor, c f , see 4.8.3 choosing a filter capacitor room temperature operation negligible external leakage on c gmxfc negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configur ed in tracking mode. see 4.3.2.2 acquisition and tracking modes . note: the inverse proportionality between the lock time and the reference frequency. in automatic bandwidth control mode, th e acquisition and lock times are quantized into units based on the reference frequency. see 4.3.2.3 manual and automatic pll bandwidth modes a certain number of clock cycles, n acq , is required to ascertain that the pll is within the tracking mode entry tolerance, ? trk , before c f c fact v dda f rdv -------------- - ?? ?? ?? = t acq v dda f rdv -------------- - ?? ?? ?? 8 k acq -------------- - ?? ?? = t al v dda f rdv -------------- - ?? ?? ?? 4 k trk -------------- ?? ?? = t lock t acq t al + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola clock generator module (cgm) 77 exiting acquisition mode. a cert ain number of clock cycles, n trk , is required to ascertain that the pll is within the lock mode entry tolerance, ? lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f rdv . also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than t lock as calculated in the previous example. in manual mode, it is usually necessary to wait considerably longer than t lock before selecting the pll clock (see 4.3.3 base clock selector circuit ) because the factors described in 4.8.2 parametric influences on reaction time may slow the lock time considerably. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 78 clock generator module (cgm) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola configuration register (config) 79 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 5. configurat ion register (config) 5.1 introduction this section describes the configuration r egister (config). this register contains bits that configure these options: resets caused by the low- voltage inhibit (lvi) module power to the lvi module computer operating properly (cop) module top-side pulse-width modulator (pwm) polarity bottom-side pwm polarity edge-aligned versus center-aligned pwms six independent pwms versus three complementary pwm pairs 5.2 functional description the configuration register (config) is used in the initialization of various options. the configuration register can be written once after each reset. all of the configuration register bits are cleared duri ng reset. since the various options affect the operation of the microcontroller unit (mcu), it is recommended that this register be written immediately after reset. the c onfiguration register is located at $001f and may be read at anytime. note: on a flash device, the options are one-time writeable by the user after each reset. the registers are not in the flash memory but are special registers containing one-time writ eable latches after each reset. upon a reset, the configuration register defaults to predetermined settings as shown in figure 5-1 . if the lvi module and the lvi reset signal are enabled, a reset occurs when v dd falls to a voltage, v lvrx , and remains at or below that level for at least nine consecutive central processor unit (cpu) cycles. once an lvi reset occurs, the mcu remains in reset until v dd rises to a voltage, v lvrx . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 80 configuration register (config) motorola 5.3 configuration register edge ? edge-align enable bit edge determines if the motor control pwm will operate in edge-aligned mode or center-aligned mode. see section 12. pulse-width modulator for motor control (pwmmc) . 1 = edge-aligned mode enabled 0 = center-aligned mode enabled botneg ? bottom-side pwm polarity bit botneg determines if the bottom-side pwms will have positive or negative polarity. see section 12. pulse-width modulator for motor control (pwmmc) . 1 = negative polarity 0 = positive polarity topneg ? top-side pwm polarity bit topneg determines if the top-side pwms will have positive or negative polarity. see section 12. pulse-width modulator for motor control (pwmmc) . 1 = negative polarity 0 = positive polarity indep ? independent mode enable bit indep determines if the motor contro l pwms will be six independent pwms or three complementary pwm pairs. see section 12. pulse-width modulator for motor control (pwmmc) . 1 = six independent pwms 0 = three complementary pwm pairs lvirst ? lvi reset enable bit lvirst enables the reset signal from the lvi module. see section 9. low-voltage inhibit (lvi) . 1 = lvi module resets enabled 0 = lvi module resets disabled lvipwr ? lvi power enable bit lvipwr enables the lvi module. see section 9. low-voltage inhibit (lvi) . 1 = lvi module power enabled 0 = lvi module power disabled address: $001f bit 7654321bit 0 read: edge botneg topneg indep lvirst lvipwr stope copd write: reset:00001100 figure 5-1. configuration register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) configuration register mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola configuration register (config) 81 stope ? stop enable bit writing a 0 or a 1 to bit 1 has no effect on mcu operation. bit 1 operates the same as the other bits within this write-once register operate. 1 = stop mode enabled 0 = stop mode disabled copd ? cop disable bit copd disables the cop module. see section 6. computer operating properly (cop) . 1 = cop module disabled 0 = cop module enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 82 configuration register (config) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola computer operating properly (cop) 83 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 6. computer op erating properly (cop) 6.1 introduction this section describes the computer o perating properly module, a free-running counter that generates a reset if allo wed to overflow. the computer operating properly (cop) module helps software reco ver from runaway code. prevent a cop reset by periodically clearing the cop counter. 6.2 functional description figure 6-1 shows the structure of the cop module. a summary of the input/output (i/o) register is shown in figure 6-2 . figure 6-1. cop block diagram copctl write cgmxclk reset vector fetch sim reset circuit sim reset status register internal reset sources(1) sim clear bits 12?4 13-bit sim counter clear all bits 6-bit cop counter copd (from config) reset copctl write clear cop module cop counter note 1. see 14.3.2 active resets from internal sources . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 84 computer operating properly (cop) motorola the cop counter is a free-running, 6-bit counter preceded by the 13-bit system integration module (sim) counter. if no t cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 cgmxclk cycles. with a 4.9152-mhz crystal, the cop timeout period is 53.3 ms. writing any value to location $ffff before overflow occurs clears the cop counter and prevents reset. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the sim reset status register (srsr). see 14.7.2 sim reset status register . note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subrouti ne could keep the cop from generating a reset even while the main program is not working properly. 6.3 i/o signals this section describes the signals shown in figure 6-1 . 6.3.1 cgmxclk cgmxclk is the crystal oscillator output signal. cgmxclk frequency is equal to the crystal frequency. 6.3.2 copctl write writing any value to the cop control register (copctl) (see 6.4 cop control register ) clears the cop counter and clears bits 12?4 of the sim counter. reading the cop control register returns the reset vector. 6.3.3 power-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 cgmxclk cycles after power-up. 6.3.4 internal reset an internal reset clears the sim counter and the cop counter. addr. register name bit 7654321bit 0 $ffff cop control register (copctl) see page 85. read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-2. cop i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola computer operating properly (cop) 85 6.3.5 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the sim counter. 6.3.6 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the configuration register (config). see section 5. configuration register (config) . 6.4 cop cont rol register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 6.5 interrupts the cop does not generate cpu interrupt requests. 6.6 monitor mode the cop is disabled in monitor mode when v hi is present on the irq pin or on the rst pin. 6.7 wait mode the wait instruction puts the mcu in low power-consumption standby mode. the cop continues to operate during wait mode. 6.8 stop mode stop mode turns off the cgmxclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-3. cop control register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 86 computer operating properly (cop) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola central processor unit (cpu) 87 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 7. central processor unit (cpu) 7.1 introduction this section describes the central pr ocessor unit (cpu08, version a). the m68hc08 cpu is an enhanced and fully obj ect-code-compatible version of the m68hc05 cpu. the cpu08 reference manual , motorola document order number cpu08rm/ad, contains a description of the cpu instruction set, addressing modes, and architecture. 7.2 features features of the cpu08 include: fully upward, object-code compatibility with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable inte rnal bus definition for extension of addressing range beyond 64 kbytes low-power wait mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 88 central processor unit (cpu) motorola 7.3 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 7-1. cpu registers 7.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the re sults of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola central processor unit (cpu) 89 7.3.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regist er, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes , the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 7.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack point er decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an i ndex register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 90 central processor unit (cpu) motorola 7.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automati cally increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. 7.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc) bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola central processor unit (cpu) 91 h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, t he highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 92 central processor unit (cpu) motorola 7.4 arithmetic/ logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock 7.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from st op mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 7.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola central processor unit (cpu) 93 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 94 central processor unit (cpu) motorola bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 table 7-1. instruction set summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola central processor unit (cpu) 95 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 table 7-1. instruction set summary (sheet 3 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 96 central processor unit (cpu) motorola cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola central processor unit (cpu) 97 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 table 7-1. instruction set summary (sheet 5 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 98 central processor unit (cpu) motorola rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 6 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola central processor unit (cpu) 99 7.8 opcode map see table 7-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 7-1. instruction set summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 100 central processor unit (cpu) motorola central processor unit (cpu) table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola external interrupt (irq) 101 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 8. external interrupt (irq) 8.1 introduction this section describes the external interr upt (irq) module, which supports external interrupt functions. 8.2 features features of the irq module include: a dedicated external interrupt pin, irq hysteresis buffers 8.3 functional description a logic 0 applied to any of the external interrupt pins can latch a cpu interrupt request. figure 8-1 shows the structure of the irq module. figure 8-1. irq module block diagram ack1 imask1 dq ck clr irq high interrupt to mode select logic irq latch request irq v dd mode1 voltage detect synchro- nizer addr. register name bit 7654321bit 0 $003f irq status/control register (iscr) see page 105. read:0000 irqf 0 imask1 mode1 write:rrrr ack1 reset:00000000 r= reserved figure 8-2. irq i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 102 external interrupt (irq) motorola interrupt signals on the irq pin are latched into the irq1 latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a logic 1 to the ack1 bit clears the irq1 latch. reset ? a reset automatically clears both interrupt latches. the external interrupt pins are falling- edge-triggered and are software-configurable to be both falling-edge and low-level-triggered. the mode1 bit in the iscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of these occur: vector fetch, software clear, or reset return of the interrupt pin to logic 1 the vector fetch or software clear can occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. when set, the imask1 bit in the iscr ma sks all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the imask bit is clear. note: the interrupt mask (i) in the condition c ode register (ccr) masks all interrupt requests, including external interrupt requests. (see figure 8-3 .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola external interrupt (irq) 103 figure 8-3. irq interrupt flowchart from reset i bit set? fetch next yes no interrupt? instruction swi instruction? rti instruction? no stack cpu registers no set i bit load pc with interrupt vector no yes unstack cpu registers execute instruction yes yes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 104 external interrupt (irq) motorola 8.4 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode1 bit is set, the irq pin is both falling-edge-sensitive and low-level- sensitive. with mode1 set, both of thes e actions must occur to clear the irq1 latch: vector fetch, software clear, or reset ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software can generate the interrupt acknowledge signal by writing a logic 1 to the ack1 bit in the interrupt status and control register (iscr). the ack1 bi t is useful in applications that poll the irq pin and require software to clear the irq1 latch. writing to the ack1 bit can also prevent spurious interrupt s due to noise. setting ack1 does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack1 bit latches another interrupt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, the irq1 latch remains set. 8.5 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode1 bit is set, the irq pin is both falling-edge-sensitive and low-level- sensitive. with mode1 set, both of thes e actions must occur to clear the irq1 latch: vector fetch, software clear, or reset ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software can generate the interrupt acknowledge signal by writing a logic 1 to the ack1 bit in the interrupt status and control register (iscr). the ack1 bi t is useful in applications that poll the irq pin and require software to clear the irq1 latch. writing to the ack1 bit can also prevent spurious interrupt s due to noise. setting ack1 does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack1 bit latches another interrupt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, the irq1 latch remains set. the vector fetch or software clear and the return of the irq pin to logic 1 can occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq status and control register mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola external interrupt (irq) 105 if the mode1 bit is clear, the irq pin is falling-edge-sens itive only. with mode1 clear, a vector fetch or software clear immediately clears the irq1 latch. use the branch if irq pin high (bih) or branch if irq pin low (bil) instruction to read the logic level on the irq pin. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 8.6 irq status an d control register the irq status and control regist er (iscr) has these functions: clears the irq interrupt latch masks irq interrupt requests controls triggering sensitivity of the irq interrupt pin ack1 ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack1 always reads as logic 0. reset clears ack1. imask1 ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask1. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode1 ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode1. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only irqf ? irq flag this read-only bit acts as a status flag, indicating an irq event occurred. 1 = external irq event occurred. 0 = external irq event did not occur. address: $003f bit 7654321bit 0 read:0000 irqf 0 imask1 mode1 write:rrrr ack1 reset:00000000 r= reserved figure 8-4. irq status and control register (iscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 106 external interrupt (irq) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola low-voltage inhibit (lvi) 107 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 9. low-volt age inhibit (lvi) 9.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. 9.2 features features of the lvi module include: programmable lvi reset programmable power consumption digital filtering of v dd pin level selectable lvi trip voltage 9.3 functional description figure 9-1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator. the lvi power bit, lvipwr, enables the lvi to monitor v dd voltage. the lvi reset bit, lvirst, enables the lvi module to generate a reset when v dd falls below a voltage, v lvrx , and remains at or below that level for nine or more consecutive cgmxclk. v lvrx and v lvhx are determined by the trpsel bit in the lviscr (see figure 9-2 ). lvipwr and lvirst are in the configuration register (config). see section 5. configuration register (config) . once an lvi reset o ccurs, the mcu remains in reset until v dd rises above a voltage, v lvrx + v lvhx . v dd must be above v lvrx + v lvhx for only one cpu cycle to bring the mcu out of reset. see 14.3.2.6 low-voltage inhibit (lvi) reset . the output of the comparator controls the state of the lviout flag in the lvi status register (lviscr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. see 19.5 dc electrical characteristics . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 108 low-voltage inhibit (lvi) motorola figure 9-1. lvi module block diagram 9.3.1 polled lvi operation in applications that can operate at v dd levels below v lvrx , software can monitor v dd by polling the lviout bit. in the config uration register, the lvipwr bit must be 1 to enable the lvi module, and the lvirst bit must be 0 to disable lvi resets. see section 5. configuration register (config) . trpsel in the lviscr selects v lvrx . 9.3.2 forced reset operation in applications that require v dd to remain above v lvrx , enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the v lvrx level and remains at or below that level for nine or more consecutive cpu cycles. in the config register, the lvipwr and lvirst bits mu st be 1s to enable the lvi module and to enable lvi resets. trpsel in the lviscr selects v lvrx . 9.3.3 false reset protection the v dd pin level is digitally filtered to r educe false resets du e to power supply noise. in order for the lvi module to reset the mcu, v dd must remain at or below v lvrx for nine or more consecutive cpu cycles. v dd must be above v lvrx + v lvhx for only one cpu cycle to bring the mcu out of reset. trpsel in the lviscr selects v lvrx + v lvhx . low v dd lvirst v dd > lvitrip = 0 v dd < lvitrip = 1 lviout lvipwr detector v dd lvi reset from config from config v dd digital filter cpu clock anlgtrip trpsel from lviscr addr. register name bit 7654321bit 0 $fe0f lvi status and control register (lviscr) see page 109. read: lviout 0 trpsel 00000 write:rr rrrrr reset:00000000 r =reserved figure 9-2. lvi i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) lvi status and control register mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola low-voltage inhibit (lvi) 109 9.3.4 lvi trip selection the trpsel bit allows the user to chose between 5 percent and 10 percent tolerance when monitoring the supply vo ltage. the 10 percent option is enabled out of reset. writing a 1 to trpsel will enable 5 percent option. note: the microcontroller is guaranteed to operate at a minimum supply voltage. the trip point (vlvr1 or vlvr2) may be lower than this. see 19.5 dc electrical characteristics . 9.4 lvi status and control register the lvi status register (lviscr) flags v dd voltages below the v lvrx level . lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v lvrx voltage for 32 to 40 cgmxclk cycles. see table 9-1 . reset clears the lviout bit. trpsel ? lvi trip select bit this bit selects the lvi trip point. reset clears this bit. 1 = 5 percent tolerance. the trip point and recovery point are determined by v lvr1 and v lvh1 , respectively. 0 = 10 percent tolerance. the trip point and recovery point are determined by v lvr2 and v lvh2 , respectively. note: if lvirst and lvipwr are 0s, note that when changing the tolerance, lvi reset will be generated if the supply voltage is below the trip point. address: $fe0f bit 7654321bit 0 read: lviout 0 trpsel 00000 write:rr rrrrr reset:00000000 r =reserved figure 9-3. lvi status and control register (lviscr) table 9-1. lviout bit indication v dd lviout at level: for number of cgmxclk cycles: v dd > v lv r x + v lv h x any 0 v dd < v lvr x < 32 cgmxclk cycles 0 v dd < v lvr x between 32 & 40 cgmxclk cycles 0 or 1 v dd < v lvr x > 40 cgmxclk cycles 1 v lv r x < v dd < v lv r x + v lv h x any previous value f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-voltage inhibit (lvi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 110 low-voltage inhibit (lvi) motorola 9.5 lvi interrupts the lvi module does not generate interrupt requests. 9.6 wait mode the wait instruction puts the mcu in low power-consumption standby mode. with the lvipwr bit in the configuration register programmed to 1, the lvi module is active after a wait instruction. with the lvirst bit in the configuration register programmed to 1, the lvi module can generate a reset and bring the mcu out of wait mode. 9.7 stop mode if enabled, the lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola input/output (i /o) ports (ports) 111 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 10. input/output (i/o) ports (ports) 10.1 introduction thirty-seven bidirectional input-output ( i/o) pins and seven input pins form six parallel ports. all i/o pins are programmable as inputs or outputs. when using the 56-pin package version: set the data direction register bits in ddrc such that bit 1 is written to a logic 1 (along with any other output bits on port c). set the data direction register bits in ddre such that bits 0, 1, and 2 are written to a logic 1 (along with any other output bits on port e). set the data directi on register bits in ddrf such th at bits 0, 1, 2, and 3 are written to a logic 1 (along with any other output bits on port f). note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although pwm6?pwm1 do not require termination for proper operation, termination reduces excess current consumpt ion and the possibility of electrostatic damage. addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (pta) see page 113. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 115. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 117. read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r reset: unaffected by reset $0003 port d data register (ptd) see page 119. read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write:rrrrrrrr reset: unaffected by reset r= reserved figure 10-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 112 input/output (i/o) ports (ports) motorola $0004 data direction register a (ddra) see page 113. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 115. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 117. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset:00000000 $0007 unimplemented $0008 port e data register (pte) see page 120. read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) see page 122. read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r reset: unaffected by reset $000a unimplemented $000b unimplemented $000c data direction register e (ddre) see page 120. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000d data direction register f (ddrf) see page 122. read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r reset: 000000 addr. register name bit 7 6 5 4 3 2 1 bit 0 r= reserved figure 10-1. i/o port register summary (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) port a mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola input/output (i /o) ports (ports) 113 10.2 port a port a is an 8-bit, general-purpose, bidirectional i/o port. 10.2.1 port a data register the port a data register (pta) contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software progra mmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. 10.2.2 data direction register a data direction register a (ddra) determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. ddra[7:0] ? data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 10-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 10-3. data direction register a (ddra) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 114 input/output (i/o) ports (ports) motorola figure 10-4 shows the port a i/o logic. figure 10-4. port a i/o circuit when bit ddrax is a logic 1, reading add ress $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 10-1 summarizes the operation of the port a pins. table 10-1. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) port b mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola input/output (i /o) ports (ports) 115 10.3 port b port b is an 8-bit, general-purpose, bidirectional i/o port that shares its pins with the analog-to-digital convertor (adc) module. 10.3.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. 10.3.2 data direction register b data direction register b (ddrb) determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 10-5. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 10-6. data direction register b (ddrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 116 input/output (i/o) ports (ports) motorola figure 10-7 shows the port b i/o logic. figure 10-7. port b i/o circuit when bit ddrbx is a logic 1, reading add ress $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 10-2 summarizes the operation of the port b pins. table 10-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) port c mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola input/output (i /o) ports (ports) 117 10.4 port c port c is a 7-bit, general-purpose, bidirect ional i/o port that shares two of its pins with the analog-to-digital convertor module (adc). 10.4.1 port c data register the port c data register (ptc) contains a data latch for each of the seven port c pins. ptc[6:0] ? port c data bits these read/write bits are software-program mable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. 10.4.2 data direction register c data direction register c (ddrc) determ ines whether each port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logic 0 disables the output buffer. ddrc[6:0] ? data direction register c bits these read/write bits control port c data direction. reset clears ddrc[6:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input address: $0002 bit 7654321bit 0 read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: r reset: unaffected by reset r = reserved figure 10-8. port c data register (ptc) address: $0006 bit 7654321bit 0 read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: r reset:00000000 r= reserved figure 10-9. data direction register c (ddrc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 118 input/output (i/o) ports (ports) motorola note: avoid glitches on port c pins by writi ng to the port c data register before changing data direction register c bits from 0 to 1. figure 10-10 shows the port c i/o logic. figure 10-10. port c i/o circuit when bit ddrcx is a logic 1, reading add ress $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading add ress $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 10-3 summarizes the operation of the port c pins. table 10-3. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrc[6:0] pin ptc[6:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[6:0] pt c[6:0] ptc[6:0] read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) port d mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola input/output (i /o) ports (ports) 119 10.5 port d port d is a 7-bit, input-only port that shar es its pins with the pulse width modulator for motor control module (pmc). the port d data register (ptd) contains a data latch for each of the seven port pins. ptd[6:0] ? port d data bits these read/write bits are software programmable. reset has no effect on port d data. figure 10-12 shows the port d input logic. figure 10-12. port d input circuit rea d ing a d dress $00 0 3 reads the volt a ge l e vel on the p i n. t a ble 10-4 summarizes the operation of the port d pins. address: $0003 bit 7654321bit 0 read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write:rrrrrrrr reset: unaffected by reset r = reserved figure 10-11. port d data register (ptd) table 10-4. port d pin functions ptd bit pin mode accesses to ptd read write x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance pin ptd[6:0] (3) 3. writing affects data regist er, but does not affect input. read ptd ($0003) ptdx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 120 input/output (i/o) ports (ports) motorola 10.6 port e port e is an 8-bit, special function port t hat shares five of its pins with the timer interface module (tim) and two of its pins with the serial communications interface module (sci). 10.6.1 port e data register the port e data register (pte) contains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits pte[7:0] are read/write, software-programmable bits. data direction of each port e pin is under the control of the corresponding bit in data direction register e. note: data direction register e (ddre) does not af fect the data direction of port e pins that are being used by the tima or timb. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. 10.6.2 data direction register e data direction register e (ddre) determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. ddre[7:0] ? data direction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input address: $0008 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset figure 10-13. port e data register (pte) address: $000c bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 10-14. data direction register e (ddre) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) port e mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola input/output (i /o) ports (ports) 121 note: avoid glitches on port e pins by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 10-15 shows the port e i/o logic. figure 10-15. port e i/o circuit when bit ddrex is a logic 1, reading add ress $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of t h e st a te of its d ata direction bit. tab l e 10-5 summarizes the o peration of the port e pins. table 10-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddre[7:0] pin pte[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddre[7:0] pte[7:0] pte[7:0] read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 122 input/output (i/o) ports (ports) motorola 10.7 port f port f is a 6-bit, special function port that shares four of its pins with the serial peripheral interface module (spi) and two pins with the seri al communications interface (sci). 10.7.1 port f data register the port f data register (ptf) contains a data latch for each of the six port f pins. ptf[5:0] ? port f data bits these read/write bits are software progr ammable. data direction of each port f pin is under the control of the corresponding bit in data direction register f. reset has no effect on ptf[5:0]. note: data direction register f (ddrf) does not a ffect the data direction of port f pins that are being used by the spi or sci module. however, the ddrf bits always determine whether reading port f returns the states of the latches or the states of the pins. 10.7.2 data direction register f data direction register f (ddrf) determines whether each port f pin is an input or an output. writing a logic 1 to a ddrf bit enables the output buffer for the corresponding port f pin; a logic 0 disables the output buffer. ddrf[5:0] ? data direction register f bits these read/write bits control port f data direction. reset clears ddrf[5:0], configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input address: $0009 bit 7654321bit 0 read: 0 0 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: r r reset: unaffected by reset r = reserved figure 10-16. port f data register (ptf) address: $000d bit 7654321bit 0 read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: r r read: 000000 r = reserved figure 10-17. data direction register f (ddrf) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) port f mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola input/output (i /o) ports (ports) 123 note: avoid glitches on port f pins by writing to the port f data register before changing data direction register f bits from 0 to 1. figure 10-18 shows the port f i/o logic. figure 10-18. port f i/o circuit when bit ddrfx is a logic 1, reading address $0009 reads the ptfx data latch. when bit ddrfx is a logic 0, reading addres s $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. tab l e 10-6 summarizes the o peration of the port f pi n s . table 10-6. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrf[6:0] pin ptf[6:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrf[6:0] ptf[6:0] ptf[6:0] read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports (ports) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 124 input/output (i/o) ports (ports) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 ? mc68HC908MR16 ? rev. 6.0 data sheet motorola power-on reset (por) 125 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 11. power-on reset (por) 11.1 introduction this section describes the power-on reset (por) module. 11.2 functional description the por module provides a known, stable signal to th e microcontroller unit (mcu) at power-on. this signal tracks v dd until the mcu generates a feedback signal to indicate that it is properly initialized. at this time, the por drives its output low. the por is not a brown-out detector, low-voltage detector, or glitch detector. v dd at the por must go completely to 0 to reset the microcontroller unit (mcu). to detect power-loss conditions, use a lo w-voltage inhibit module (lvi) or other suitable circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . power-on reset (por) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 126 power-on reset (por) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 127 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 12. pulse-width modula tor for motor control (pwmmc) 12.1 introduction this section describes the pulse-width modulator for motor control (pwmmc, version a). the pwm module can generate three complementary pwm pairs or six independent pwm signals. these pwm signals can be center-aligned or edge-aligned. a block diagram of the pwm module is shown in figure 12-2 . a12-bit timer pwm counter is common to all six channels. pwm resolution is one clock period for edge-aligned operation and two clock periods for center-aligned operation. the clock period is dependent on the internal operating frequency (f op ) and a programmable prescaler. the highest resolution for edge-aligned operation is 125 ns (f op = 8 mhz). the highest resolution for center-aligned operation is 250 ns (f op =8mhz). when generating complementary pwm signals, the module features automatic dead-time insertion to the pwm output pairs and transparent toggling of pwm data based upon sensed motor phase current polarity. a summary of the pwm registers is shown in figure 12-3 . 12.2 features features of the pwmmc include: three complementary pwm pairs or six independent pwm signals edge-aligned pwm signals or center-aligned pwm signals pwm signal polarity control 20-ma current sink capability on pwm pins manual pwm output control through software programmable fault protection complementary mode featuring: ? dead-time insertion ? separate top/bottom pulse width correction via current sensing or programmable software bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 128 pulse-width modulator for mo tor control (pwmmc) motorola pulse-width modulator fo r motor control (pwmmc) figure 12-1. block diagram highlighting pwmmc block and pins clock generator module system integration module serial communications interface module serial peripheral interface module (2) timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 112 bytes user flash ? 32,256 bytes user ram ? 768 bytes monitor rom ? 240 bytes user flash vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq v ss v dd v ddad pta7?pta0 pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b (1) pte1/tch0b (1) pte0/tclkb (1) ptf5/txd ptf4/rxd ptf3/miso (1) ptf2/mosi (1) ptf1/ss (1) ptf0/spsck (1) timer interface module b pulse-width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9(1) ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssad v dda v ssa (3) pwmgnd v refl (3) v refh notes: 1. these pins are not avail able in the 56-pin sdip package. 2. this module is not avail able in the 56-pin sdip package. 3. in the 56-pin sdip package, these pins are bonded together. single break module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) features mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 129 figure 12-2. pwm module block diagram pwm1 pin pwm2 pin pwm channels 3 and 4 pwm3 pin pwm4 pin pwm channels 5 and 6 pwm5 pin pwm6 pin timebase cpu bus output control coil current polarity pins 3 4 fault interrupt pins 12 control logic block 8 pwm channels 1 and 2 fault protection addr. register name bit 7 6 5 4 3 2 1 bit 0 $0020 pwm control register 1 (pctl1) see page 158. read: disx disy pwmint pwmf isens1 isens0 ldok pwmen write: reset: 0 0 0 0 0 0 0 0 $0021 pwm control register 2 (pctl2) see page 160. read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset: 0 0 0 0 0 0 0 0 $0022 fault control register (fcr) see page 162. read: fint4 fmode4 fint3 fmode3 fint2 fmode2 fint1 fmode1 write: reset: 0 0 0 0 0 0 0 0 $0023 fault status register (fsr) see page 164. read: fpin4 fflag4 fpin3 fflag3 fpin2 fflag2 fpin1 fflag1 write: reset: u 0 u 0 u 0 u 0 r = reserved bold = buffered x = indeterminate figure 12-3. register summary (sheet 1 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 130 pulse-width modulator for mo tor control (pwmmc) motorola $0024 fault acknowledge register (ftack) see page 165. read: 0 0 dt6 dt5 dt4 dt3 dt2 dt1 write: ftack4 ftack3 ftack2 ftack1 reset: 0 0 0 0 0 0 0 0 $0025 pwm output control register (pwmout) see page 166. read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset: 0 0 0 0 0 0 0 0 $0026 pwm counter register high (pcnth) see page 156. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0027 pwm counter register low (pcntl) see page 156. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0028 pwm counter modulo register high (pmodh) see page 156. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 x x x x $0029 pwm counter modulo register low (pmodl) see page 156. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: x x x x x x x x $002a pwm 1 value register high (pval1h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002b pwm 1 value register low (pval1l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $002c pwm 2 value register high (pval2h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002d pwm 2 value register low (pval2l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved bold = buffered x = indeterminate figure 12-3. register summary (sheet 2 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) features mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 131 $002e pwm 3 value register high (pval3h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $002f pwm 3 value register low (pval3l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0030 pwm 4 value register high (pval4h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0031 pwm 4 value register low (pval4l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0032 pwm 5 value register high (pval5h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0033 pwm 5 value register low (pval5l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0034 pwm 6 value register high (pval6h) see page 157. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0035 pwm 6 value register low (pmval6l) see page 157. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0036 dead-time write-once register (deadtm) see page 162. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0037 pwm disable mapping write-once register (dismap) see page 162. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved bold = buffered x = indeterminate figure 12-3. register summary (sheet 3 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 132 pulse-width modulator for mo tor control (pwmmc) motorola 12.3 timebase this section provides a discussion of the timebase. 12.3.1 resolution in center-aligned mode, a 12-bit up/down counter is used to create the pwm period. therefore, the pwm resolution in center-aligned mode is two clocks (highest resolution is 250 ns @ f op = 8 mhz) as shown in figure 12-4 . the up/down counter uses the value in the ti mer modulus register to determine its maximum count. the pwm period will equal: [(timer modulus) x (pwm clock period) x 2]. figure 12-4. center-aligned pwm (positive polarity) up/down counter modulus = 4 pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 period = 8 x (pwm clock period) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) timebase mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 133 for edge-aligned mode, a 12-bit up-only counter is used to create the pwm period. therefore, the pwm resolution in edge-aligned mode is one clock (highest resolution is125 ns @ f op = 8 mhz) as shown in figure 12-5 . again, the timer modulus register is used to determi ne the maximum count. the pwm period will equal: (timer modulus) x (pwm clock period) center-aligned operation versus edge-a ligned operation is determined by the option edge. see 5.2 functional description . figure 12-5. edge-aligned pwm (positive polarity) up-only counter modulus = 4 pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 period = 4 x (pwm clock period) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 134 pulse-width modulator for mo tor control (pwmmc) motorola 12.3.2 prescaler to permit lower pwm frequencies, a prescaler is provided which will divide the pwm clock frequency by 1, 2, 4, or 8. table 12-1 shows how setting the prescaler bits in pwm control register 2 affects the pwm clock frequency. this prescaler is buffered and will not be used by the pwm generator until the ldok bit is set and a new pwm reload cycle begins. 12.4 pwm generators pulse-width modulator (pwm) generators are discussed in this subsection. 12.4.1 load operation to help avoid erroneous pulse widths and pwm periods, the modulus, prescaler, and pwm value registers are buffered. new pwm values, counter modulus values, and prescalers can be loaded from their buffers into the pwm module every one, two, four, or eight pwm cycles. ldfq1 and ldfq0 in pwm control register 2 are used to control this reload frequency, as shown in table 12-2 . when a reload cycle arrives, regardless of whether an actual re load occurs (as determined by the ldok bit), the pwm reload flag bit in pwm control register 1 will be set. if the pwmint bit in pwm control register 1 is set, a cpu interrupt request will be generated when pwmf is set. software can use this interrupt to calculate new pwm parameters in real time for the pwm module. table 12-1. pwm prescaler prescaler bits prsc1 and prsc0 pwm clock frequency 00 f op 01 f op /2 10 f op /4 11 f op /8 table 12-2. pwm reload frequency reload frequency bits ldfq1 and ldfq0 pwm reload frequency 00 every pwm cycle 01 every 2 pwm cycles 10 every 4 pwm cycles 11 every 8 pwm cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) pwm generators mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 135 for ease of software, the ldfqx bits are buffered. when the ldfqx bits are changed, the reload frequency will not change until the previous reload cycle is completed. see figure 12-6 . note: when reading the ldfqx bits, the value is the buffered value (for example, not necessarily the value being acted upon). figure 12-6. reload frequency change pwmint enables cpu interrupt requests as shown in figure 12-7 . when this bit is set, cpu interrupt requests are generated when the pwmf bit is set. when the pwmint bit is clear, pwm interrupt requests are inhibited. pwm reloads will still occur at the reload rate, but no interrupt requests will be generated. figure 12-7. pwm interrupt requests to prevent a partial reload of pwm parameters from occurring while the software is still calculating them, an interlock bit controlled from software is provided. this bit informs the pwm module that all the pwm parameters have been calculated, and it is ?okay? to use them. a new modulus, prescaler, and/or pwm value cannot be loaded into the pwm module until the ldok bit in pwm control register 1 is set. when the ldok bit is set, these new val ues are loaded into a second set of registers and used by the pwm generator at the beginning of the next pwm reload cycle as shown in figure 12-8 , figure 12-9 , figure 12-10 , and figure 12-11 . after these values are loaded, the ldok bit is cleared. note: when the pwm module is enabled (via the pw men bit), a load will occur if the ldok bit is set. even if it is not set, an in terrupt will occur if the pwmint bit is set. reload reload reload reloadreloadreload reload change reload frequency to every 4 cycles change reload frequency to every cycle latch v dd cpu interrupt reset d ck pwmint pwmf pwm reload read pwmf as 1, write pwmf as 0 or reset request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 136 pulse-width modulator for mo tor control (pwmmc) motorola to prevent this, the software should clear the pwmint bit before enabling the pwm module. figure 12-8. center-aligned pwm value loading figure 12-9. center-aligned loading of modulus figure 12-10. edge-aligned pwm value loading ldok = 1 modulus = 3 pwm value = 1 ldok = 1 modulus = 3 pwm value = 2 up/down counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 3 pwm value = 2 ldok = 0 modulus = 3 pwm value = 1 pwmf set pwmf set pwmf set pwmf set ldok = 1 pwm value = 1 modulus = 2 ldok = 1 pwm value = 1 modulus = 3 ldok = 1 pwmvalue = 1 modulus = 2 ldok = 1 pwm value = 1 modulus = 1 ldok = 0 pwm value = 1 modulus = 2 up/down counter pwm ldfq1:ldfq0 = 00 (reload every cycle) pwmf set pwmf set pwmf set pwmf set pwmf set ldok = 1 modulus = 3 pwm value = 1 ldok = 1 modulus = 3 pwm value = 2 up-only counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 3 pwm value = 2 ldok = 0 modulus = 3 pwm value = 1 ldok = 0 modulus = 3 pwm value = 1 pwmf set pwmf set pwmf set pwmf set pwmf set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) pwm generators mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 137 figure 12-11. edge-aligned modulus loading 12.4.2 pwm data overflow and underflow conditions the pwm value registers are 16-bit registers. although the counter is only 12 bits, the user may write a 16-bit signed value to a pwm value register. as shown in figure 12-4 and figure 12-5 , if the pwm value is less than or equal to zero, the pwm will be inactive for the entire period. conversely, if the pwm value is greater than or equal to the timer modulus, the pwm will be active for the entire period. refer to table 12-3 . note: the terms ?active? and ?inactive? refer to the asserted and negated states of the pwm signals and should not be confused with the high-impedance state of the pwm pins. ldok = 1 modulus = 3 pwm value = 2 ldok = 1 modulus = 4 pwm value = 2 ldok = 1 modulus = 2 pwm value = 2 up-only counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 1 pwm value = 2 pwmf set pwmf set pwmf set pwmf set table 12-3. pwm data overflow and underflow conditions pwmvalxh:pwmvalxl con dition pwm value used $0000?$0fff normal per register contents $1000?$7fff overflow $fff $8000?$ffff underflow $000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 138 pulse-width modulator for mo tor control (pwmmc) motorola 12.5 output control this subsection discus ses output control. 12.5.1 selecting six independent pw ms or three complementary pwm pairs the pwm outputs can be configured as six independent pwm channels or three complementary channel pairs. the option indep determines which mode is used (see 5.2 functional description ). if complementary operation is chosen, the pwm pins are paired as shown in figure 12-12 . operation of one pair is then determined by one pwm value register. this type of operation is meant for use in motor drive circuits such as the one in figure 12-13 . when complementary operation is used, two additional features are provided: dead-time insertion separate top/bottom pulse width correct ion to correct for distortions caused by the motor drive characteristics if independent operation is chosen, each pw m has its own pwm value register. figure 12-12. complementary pairing pwm value register pwms 1 and 2 pwms 3 and 4 pwms 5 and 6 output control pwm value register pwm value register pwm1 pin pwm2 pin pwm3 pin pwm4 pin pwm5 pin pwm6 pin polarity & dead-time insertion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) output control mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 139 figure 12-13. typical ac motor drive 12.5.2 dead-time insertion as shown in figure 12-13 , in complementary mode, each pwm pair can be used to drive top-side/bottom-side transistors. when controlling dc-to-ac inverters such as this, the top and bottom pwms in one pair should never be active at the same time. in figure 12-13 , if pwm1 and pwm2 were on at the same time, large currents would flow through the two transistors as they discharge the bus capacitor. the igbts could be weakened or destroyed. simply forcing the two pwms to be inversio ns of each other is not always sufficient. since a time delay is associated with turning off the transistors in the motor drive, there must be a dead-time between the deactivation of one pwm and the activation of the other. a dead-time can be specified in the dead-time write-once register. this 8-bit value specifies the number of cpu clock cycles to use for the dead-time. the dead-time is not affected by changes in the pwm period caused by the prescaler. dead-time insertion is achieved by feeding the top pwm outputs of the pwm generator into dead-time generators, as shown in figure 12-14 . current sensing determines which pwm value of a pwm gener ator pair to use for the top pwm in the next pwm cycle. see 12.5.3 top/bottom correction with motor phase current polarity sensing . when output control is enabled, the odd out bits, rather than the pwm generator outputs, are fed into the dead-time generators. see 12.5.5 pwm output port control . pwm 1 pwm 2 pwm 3 pwm 4 pwm 5 pwm 6 ac to motor inputs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 140 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-14. dead-time generators whenever an input to a dead-time generator transitions, a dead-time is inserted (for example, both pwms in the pair are fo rced to their inactive state). the bottom pwm signal is generated from the top pwm and the dead-time. in the case of output control enabled, the odd outx bits control the top pwms, the even outx bits control the bottom pwms with respect to the odd outx bits (see table 12-6 ). figure 12-15 shows the effects of the dead-time insertion. as seen in figure 12-15 , some pulse width distortion occurs when the dead-time is inserted. the active pulse widths are reduced. for example, in figure 12-15 , when the pwm value register is equal to two, the ideal waveform (with no dead-time) has pulse widths equal to four. ho wever, the actual pulse widths shrink to two after a dead-time of two was inserted. in this example, with the prescaler set to divide by one and center-aligned operation selected, this distortion can be compensated for by adding or subtracting half the dead-time value to or from the pwm register value. this correction is further described in 12.5.3 top/bottom correction with motor phase current polarity sensing . further examples of dead-time insertion are shown in figure 12-16 and figure 12-17 . figure 12-16 shows the effects of dead-time insertion at the duty cycle fault polarity/output drive pwmgen<1:6> pwmpair12 pwmpair34 pwmpair56 dead-time top/bottom generation postdt (top) top/bottom generation top/bottom generation top bottom top bottom top bottom pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 6 mux pwm (top) outx select predt (top) mux pwm (top) outx select predt (top) mux pwm (top) outx select predt (top) dead-time dead-time postdt (top) dead-time dead-time postdt (top) dead-time (top) (top) (top) (pwm1) (pwm2) (pwm3) (pwm4) (pwm5) (pwm6) output control out1 out3 out5 outctl out2 out4 out6 (outctl) current sensing pwm generator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) output control mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 141 boundaries (near 0 percent and 100 percent duty cycles). figure 12-17 shows the effects of dead-time insertion on pulse widths smaller than the dead-time. figure 12-15. effects of dead-time insertion figure 12-16. dead-time at duty cycle boundaries pwm value = 2 pwm value = 2 pwm value = 3 pwm1 w/ pwm2 w/ pwm1 w/ pwm2 w/ no dead-time no dead-time dead-time = 2 dead-time = 2 2 2 2 2 up/down counter modulus = 4 22 up/down counter modulus = 3 pwm value = 1 pwm value = 3 pwm value = 3 pwm1 w/ no dead-time pwm2 w/ no dead-time pwm1 w/ dead-time = 2 pwm2 w/ dead-time = 2 2 2 2 2 pwm value = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 142 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-17. dead-time and small pulse widths 12.5.3 top/bottom correction with motor phase current polarity sensing ideally, when complementary pairs are used, the pwm pairs are inversions of each other, as shown in figure 12-18 . when pwm1 is active, pwm2 is inactive, and vice versa. in this case, the motor terminal voltage is never allowed to float and is strictly controlled by the pwm waveforms. figure 12-18. ideal complementary operation (dead-time = 0) 3 3 3 3 3 3 up/down counter moudulus = 3 pwm value = 2 pwm value = 3 pwm value = 2 pwm value = 1 pwm1 w/ no dead-time pwm2 w/ no dead-time pwm1 w/ dead-time = 3 pwm2 w/ dead-time = 3 up/down counter modulus = 4 pwm value = 1 pwm1 pwm2 pwm value = 2 pwm3 pwm4 pwm value = 3 pwm5 pwm6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) output control mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 143 however, when dead-time is inserted, the motor voltage is allowed to float momentarily during the dead-time interval, creating a distortion in the motor current waveform. this distortion is aggravated by dissimilar turn-on and turn-off delays of each of the transistors. for a typical motor drive inverter as shown in figure 12-13 , for a given top/bottom transistor pair, only one of the transistors will be effective in controlling the output voltage at any given time depending on the direction of the motor current for that pair. to achieve distortion correction, one of two different correction factors must be added to the desired pwm value, depending on whether the top or bottom transistor is controlling the output voltage. therefore, the software is responsible for calculating both compensated pwm values and placing them in an odd/even pwm register pair. by supplying the pwm module with information regarding which transistor (top or bottom) is controlling the output voltage at any given time (for instance, the current polarity for that motor phase), the pwm module selects either the odd or even numbered pwm value register to be used by the pwm generator. current sensing or programmable software bits are then used to determine which pwm value to use. if the current sensed at the motor for that pwm pair is positive (voltage on current pin isx is low) or bit ipolx in pwm control register 2 is low, the top pwm value is used for the pwm pair. likewise, if the current sensed at the motor for that pwm pair is negative (voltage on current pin isx is high) or bit ipolx in pwm control register 2 is high, the bottom pwm value is used. see table 12-4 . note: this text assumes the user will provide current sense circuitry which causes the voltage at the corresponding input pin to be low for positive current and high for negative current. see figure 12-19 for current convention. in addition, it assumes the top pwms are pwms 1, 3, and 5 while the bottom pwms are pwms 2, 4, and 6. table 12-4. current sense pins current sense pin or bit voltage on current sense pin or ipolx bit pwm value register used pwms affected is1 or ipol1 logic 0 pwm value register 1 pwms 1 and 2 is1 or ipol1 logic 1 pwm value register 2 pwms 1 and 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 144 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-19. current convention to allow for correction based on different current sensing methods or correction controlled by software, the isens1 and isens0 bits in pwm control register 1 are provided to choose the correction method. these bits provide correction according to table 12-5 . if correction is to be done in software or is not necessary, setting isens1:isens0 = 00 or = 01 causes the co rrection to be based on bits ipol1, ipol2, and ipol3 in pwm control register 2. if correction is not required, the user can initialize the ipolx bits and then only load one pwm value register per pwm pair. to allow the user to use a current sense scheme based upon sensed phase voltage during dead-time, setting isens1:isens0 = 10 causes the polarity of the ix pin to be latched when both the top and bottom pwms are off (for example, during the dead-time). at the 0 percent and 100 percent duty cycle boundaries, there is no dead-time so no new current value is sensed. to accommodate other current sensing schemes, setting isens1:isens0 = 11 causes the polarity of the current sense pin to be latched half-way into the pwm cycle in center-aligned mode and at the end of the cycle in edge-aligned mode. therefore, even at 0 percent and 100 percent duty cycle, the current is sensed. table 12-5. correction methods current correction bits isens1 and isens0 correction method 00 01 bits ipol1, ipol2, and ipol3 used for correction 10 current sensing on pins is1 , is2 , and is3 occurs during the dead-time. 11 current sensing on pins is1 , is2 , and is3 occurs at the half cycle in center-aligned mode and at the end of the cycle in edge-aligned mode. i+ i- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) output control mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 145 distortion correction is only available in complementary mode. at the beginning of the pwm period, the pwm uses this latched current value or polarity bit to decide whether the top pwm value or bottom pwm value is used. figure 12-20 shows an example of top/bottom correction for pwms 1 and 2. note: the ipolx bits and the values latched on the isx pins are buffered so that only one pwm register is used per pwm cycle. if the ipolx bits or the current sense values change during a pwm period, this new value will not be used until the next pwm period. the isensx bits are not buffered; therefore, changing the current sensing method could affect the present pwm cycle. when the pwm is first enabled by setting pwmen, pwm value registers 1, 3, and 5 will be used if the isensx bits are configured for current sensing correction. this is because no current w ill have previous ly been sensed. figure 12-20. top/bottom correction for pwms 1 and 2 12.5.4 output polarity the output polarity of the pwms is determined by two options: topneg and botneg. the top polarity option, topneg, controls the polarity of pwms 1, 3, and 5. the bottom polarity option, botneg, controls the polarity of pwms 2, 4, and 6. positive polarity means that when the pwm is active, the pwm output is high. conversely, negative polarity means that when the pwm is active, pwm output is low. see figure 12-21 . note: both bits are found in the config regist er, which is a write-once register. this reduces the chances of the software inadvertently changing the polarity of the pwm signals and possibly damaging the motor drive hardware. pwm1 pwm2 pwm value reg. 1 = 1 pwm value reg. 2 = 2 is1 positive is1 positive is1 negative is1 negative pwm = 1 pwm = 1 pwm = 2 pwm = 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 146 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-21. pwm polarity 12.5.5 pwm output port control conditions may arise in which the pwm pins need to be individually controlled. this is made possible by the pwm output control register (pwmout) shown in figure 12-22 . up/down counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 up-only counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 center-aligned positive polarity edge-aligned positive polarity up/down counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 up-only counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 center-aligned negative polarity edge-aligned negative polarity address: $0025 bit 7654321bit 0 read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset:00000000 = unimplemented figure 12-22. pwm output control register (pwmout) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) output control mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 147 if the outctl bit is set, the pwm pins ca n be controlled by the outx bits. these bits behave according to table 12-6 . when outctl is set, the polarity options toppol and botpol will still affect the outputs. in addition, if complementary operation is in use, the pwm pairs will not be allowed to be active simultaneously , and dead-time will still not be violated. when outctl is set and complementary operation is in use, the odd outx bits are inputs to the dead-time generators as shown in figure 12-15 . dead-time is inserted whenever the odd outx bit toggles as shown in figure 12-23 . although dead-time is not inserted when the even outx bits change, there will be no dead-time violation as shown in figure 12-24 . setting the outctl bit does not disable the pwm generator and current sensing circuitry. they continue to run, but are no longer controlling the output pins. in addition, outctl will control the pwm pins even when pwmen = 0. when outctl is cleared, the outputs of the pwm generator become the inputs to the dead-time and output circuitry at the beginning of the next pwm cycle. note: to avoid an unexpected dead-time occurrence, it is recommended that the outx bits be cleared prior to entering and prio r to exiting individual pwm output control mode. table 12-6. outx bits outx bit complementary mode independent mode out1 1 ? pwm1 is active. 0 ? pwm1 is inactive. 1 ? pwm1 is active. 0 ? pwm1 is inactive. out2 1 ? pwm2 is complement of pwm 1. 0 ? pwm2 is inactive. 1 ? pwm2 is active. 0 ? pwm2 is inactive. out3 1 ? pwm3 is active. 0 ? pwm3 is inactive. 1 ? pwm3 is active. 0 ? pwm3 is inactive. out4 1 ? pwm4 is complement of pwm 3. 0 ? pwm4 is inactive. 1 ? pwm4 is active. 0 ? pwm4 is inactive. out5 1 ? pwm5 is active. 0 ? pwm5 is inactive. 1 ? pwm5 is active. 0 ? pwm5 is inactive. out6 1 ? pwm 6 is complement of pwm 5. 0 ? pwm6 is inactive. 1 ? pwm6 is active. 0 ? pwm6 is inactive. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 148 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-23. dead-time insertion during outctl = 1 figure 12-24. dead-time insertion during outctl = 1 up/down counter modulus = 4 pwm1 pwm2 dead-time = 2 outctl out1 out2 2 pwm1/pwm2 2 2 dead-time inserted as part of normal pwm operation as controlled by current sensing and pwm generator dead-time inserted due to setting of out1 bit dead-time inserted due to clearing of out1 bit pwm value = 3 dead-time up/down counter modulus = 4 dead-time = 2 outctl pwm1 pwm2 out1 out2 2 pwm1/pwm2 2 2 pwm value = 3 dead-time inserted because when outctl was set, the state of out1 was such that pwm1 was directed to toggle dead-time inserted because out1 toggles, directing pwm1 to toggle no dead-time inserted because out1 is not toggling dead-time 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) fault protection mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 149 12.6 fault protection conditions may arise in the external dr ive circuitry which require that the pwm signals become inactive immediately, such as an overcurrent fault condition. furthermore, it may be desirable to selectively disable pwm(s) solely with software. one or more pwm pins can be disabled (forc ed to their inactive state) by applying a logic high to any of the four external faul t pins or by writing a logic high to either of the disable bits (disx and disy in pwm control register 1). figure 12-26 shows the structure of the pwm disabling scheme. while the pwm pins are disabled, they are forced to their inactive state. the pwm generator continues to run ? only the output pins are disabled. to allow for different motor configurati ons and the controlling of more than one motor, the pwm disabling function is organized as two banks, bank x and bank y. bank information combines with informat ion from the disable mapping register to allow selective pwm disabling. fault pin 1, fault pin 2, and pwm disable bit x constitute the disabling function of bank x. fault pin 3, fault pin 4, and pwm disable bit y constitute the dis abling function of bank y. figure 12-25 and figure 12-27 show the disable mapping write-once regi ster and the decoding scheme of the bank which selectively disables pwm(s) . when all bits of the disable mapping register are set, any disable c ondition will disable all pwms. a fault can also generate a cpu interrupt. each fault pin has its own interrupt vector. 12.6.1 fault condition input pins a logic high level on a fault pin disables the respective pwm(s) determined by the bank and the disable mapping register. each fault pin incorporates a filter to assist in rejecting spurious faults. all of the ex ternal fault pins are software-configurable to re-enable the pwms either with the fault pin (automatic mode) or with software (manual mode). each fault pin has an asso ciated fmode bit to control the pwm re-enabling method. automatic mode is sele cted by setting the fmodex bit in the fault control register. manual mode is selected when fmodex is clear. address: $0037 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 12-25. pwm disable mapping write-once register (dismap) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 150 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-26. pwm disabling scheme fint2 cycle start logic high for fault bank x fmode2 disx clear by writing 1 to ftack4 interrupt request shot sq r sq r sq r one fpin2 fflag2 manual mode auto mode software x disable fault pin 2 disable the example is of fault pin 2 with disx. fault pin 4 wit h disy is logically similar and affects bank y disable. note: in manual mode (fmode = 0), faults 2 and 4 may be clea red only if a logic level low at the input of the fault pin is present. fault pin2 disable two sample filter fault pin1 fint1 cycle start logic high for fault bank x disable fmode1 clear by writing 1 to ftack1 interrupt request two shot sq r sq r sample filter one fflag1 manual mode auto mode fault pin 1 disable the example is of fault pin 1. fault pin 3 is logically similar and affects bank y disable. note: in manual mode (fmode = 0), faults 1 and 3 may be cleared regardless of the logic level at the input of the fault pin. fpin1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) fault protection mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 151 figure 12-27. pwm disabling decode scheme 12.6.1.1 fault pin filter each fault pin incorporates a filter to a ssist in determining a genuine fault condition. after a fault pin has been logic low for one cpu cycle, a rising edge (logic high) will be synchronously sampled once per cpu cycle for two cycles. if both samples are detected logic high, the corresponding fp in bit and fflag bit will be set. the fpin bit will remain set until the co rresponding fault pin is logic low and synchronously sampled once in the following cpu cycle. 12.6.1.2 automatic mode in automatic mode, the pwm(s) are disa bled immediately once a filtered fault condition is detected (logic high). the pwm(s) remain disabled until the filtered fault condition is cleared (logic low) and a new pwm cycle begins as shown in figure 12-28 . clearing the corresponding fflagx event bit will not enable the pwms in automatic mode. bit 7 bit 3 bit 0 bit 1 bit 2 bit 4 bit 5 bit 6 bank x disable disable disable disable disable disable disable disable bank y pwm pin 1 pwm pin 2 pwm pin 3 pwm pin 4 pwm pin 5 pwm pin 6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 152 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-28. pwm disabling in automatic mode the filtered fault pin?s logic state is reflected in the respective fpinx bit. any write to this bit is overwritten by the pin stat e. the fflagx event bit is set with each rising edge of the respective fault pin afte r filtering has been applied. to clear the fflagx bit, the user must write a 1 to the corresponding ftackx bit. if the fintx bit is set, a fault condition resulting in setting the corresponding fflag bit will also latch a cpu interrupt request. the interrupt request latch is not cleared until one of these actions occurs: the fflagx bit is cleared by writing a 1 to the corresponding ftackx bit. the fintx bit is cleared. this will not clear the fflagx bit. a reset automatically clears all four interrupt latches. if prior to a vector fetch, the interrupt r equest latch is cleared by one of the actions listed, a cpu interrupt will no longer be requested. a vector fetch does not alter the state of the pwms, the fflagx event flag, or fintx. note: if the fflagx or fintx bits are not cleared during the interrupt service routine, the interrupt request latch will not be cleared. 12.6.1.3 manual mode in manual mode, the pwm(s) are dis abled immediately once a filtered fault condition is detected (logic high). t he pwm(s) remain disabled until software clears the corresponding fflagx event bit and a new pwm cycle begins. in manual mode, the fault pins are grouped in pairs, each pair sharing common functionality. a fault condition on pins 1 and 3 may be cleared, allowing the pwm(s) to enable at the start of a pwm cycle regardless of the logic level at the fault pin. see figure 12-29 . a fault condition on pins 2 and 4 can only be cleared, allowing the pwm(s) to enable, if a logic low level at the fault pin is present at the start of a pwm cycle. see figure 12-30 . the function of the fault control and event bits is the same as in automatic mode except that the pwms are not re-enabled until the fflagx event bit is cleared by writing to the ftackx bit and the filtered fault condition is cleared (logic low). pwm(s) enabled pwm(s) enabled pwm(s) disabled (inactive) filtered fault pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) fault protection mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 153 figure 12-29. pwm disabling in manual mode (example 1) figure 12-30. pwm disabling in manual mode (example 2) 12.6.2 software output disable setting pwm disable bit disx or disy in pwm control register 1 immediately disables the corresponding pwm pins as determined by the bank and disable mapping register. the pwm pin(s) remain disabled until the pwm disable bit is cleared and a new pwm cycle begins as shown in figure 12-31 . setting a pwm disable bit does not latch a cpu interrupt request, and there are no event flags associated with the pwm disable bits. 12.6.3 output port control when operating the pwms using the outx bits (outctl = 1), fault protection applies as described in this section. d ue to the absence of periodic pwm cycles, fault conditions are cleared upon each cpu cycle and the pwm outputs are re-enabled, provided all fault cl earing conditions are satisfied. pwm(s) enabled pwm(s) enabled pwm(s) disabled fflagx cleared filtered fault pin 1 or 3 pwm(s) enabled pwm(s) enabled pwm(s) disabled fflagx cleared filtered fault pin 2 or 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 154 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-31. pwm software disable 12.7 initialization and the pwmen bit for proper operation, all registers should be initialized and the ldok bit should be set before enabling the pwm via the pwmen bit. when the pwmen bit is first set, a reload will occur immediately, setting the pwmf flag and generating an interrupt if pwmint is set. in addition, in complementary mode, pwm value registers 1, 3, and 5 will be used for the first pwm cycle if current sensing is selected. note: if the ldok bit is not set when pwmen is set after a reset , the prescaler and pwm values will be 0, but the modulus will be unknown. if the ldok bit is not set after the pwmen bit has been cleared then set (without a reset ), the modulus value that was last loaded will be used. if the dead-time register (deadtm) is changed after pwmen or outctl is set, an improper dead-time insertion could occur. however, the dead-time can never be shorter than the specified value. because of the equals-comparator architecture of this pwm, the modulus = 0 case is considered illegal. therefore, the modulus register is not reset, and a modulus value of 0 will result in waveforms incons istent with the other modulus waveforms. see 12.9.2 pwm counter modulo registers . when pwmen is set, the pwm pins chang e from high impedance to outputs. at this time, assuming no fault condition is present, the pwm pins will drive according to the pwm values, polarity, and d ead-time. see the timing diagram in figure 12-32 . pwm(s) enabled pwm(s) enabled pwm(s) disabled disable bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) pwm operation in wait mode mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 155 figure 12-32. pwmen and pwm pins when the pwmen bit is cleared, this will occur: pwm pins will be three-stated unless outctl = 1. pwm counter is cleared and will not be clocked. internally, the pwm generator will force its outputs to 0 to avoid glitches when the pwmen is set again. when pwmen is cleared, these features remain active: all fault circuitry manual pwm pin control via the pwmout register dead-time insertion when pwm pins change via the pwmout register note: the pwmf flag and pending cpu interrupts are not cleared when pwmen = 0. 12.8 pwm operation in wait mode when the microcontroller is put in low-power wait mode via the wait instruction, all clocks to the pwm module will continue to run. if an interrupt is issued from the pwm module (via a reload or a fault), the microcontroller will exit wait mode. clearing the pwmen bit before entering wait mode will reduce power consumption in wait mode because the counter, prescaler divider, and ldfq divider will no longer be clocked. in addition, power wi ll be reduced because the pwms will no longer toggle. 12.9 control logic block this subsection provides a descrip tion of the control logic block. 12.9.1 pwm counter registers the pwm counter registers (pcnth and pcntl) display the 12-bit up/down or up-only counter. when the high byte of the counter is read, the lower byte is latched. pcntl will hold this latc hed value until it is read. see figure 12-33 and figure 12-34 . cpu clock pwmen pwm pins drive according to pwm value, polarity, and dead-time hi-z if outctl = 0 hi-z if outctl = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 156 pulse-width modulator for mo tor control (pwmmc) motorola 12.9.2 pwm counter modulo registers the pwm counter modulus registers (pmodh and pmodl) hold a 12-bit unsigned number that determines the maximum count for the up/down or up-only counter. in center-aligned mode, the pwm period wi ll be twice the modulus (assuming no prescaler). in edge-aligned mode, the pwm period will equal the modulus. see figure 12-35 and figure 12-36 . address: $0026 bit 7654321bit 0 read:0000bit 11bit 10bit 9bit 8 write: reset:00000000 = unimplemented figure 12-33. pwm counter register high (pcnth) address: $0027 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 12-34. pwm counter register low (pcntl) address: $0028 bit 7654321bit 0 read:0000 bit 11 bit 10 bit 9 bit 8 write: reset:0000 xxxx = unimplemented x = indeterminate figure 12-35. pwm counter modulo register high (pmodh) address: $0029 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:xxxxxxxx x = indeterminate figure 12-36. pwm counter modulo register low (pmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) control logic block mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 157 to avoid erroneous pwm periods, this value is buffered and will not be used by the pwm generator until the ldok bit has been set and the next pwm load cycle begins. note: when reading this register, the value read is the buffer (not necessarily the value the pwm generator is currently using). because of the equals-comparator architecture of this pwm, the modulus = 0 case is considered illegal. therefore, the modulus register is not reset, and a modulus value of 0 will result in waveforms incons istent with the other modulus waveforms. if a modulus of 0 is loaded, the counter will continually count down from $fff. this operation will not be tested or guaranteed (the user should consider it illegal). however, the dead-time constraints and fault conditions will still be guaranteed. 12.9.3 pwmx value registers each of the six pwms has a 16-bit pwm value register. the 16-bit signed value stored in this regi ster determines the duty cycle of the pwm. the duty cycle is defined as: (pwm value/modulus) x 100. writing a number less than or equal to 0 causes the pwm to be off for the entire pwm period. writing a number greater than or equal to the 12-bit modulus causes the pwm to be on for the entire pwm period. if the complementary mode is selected, the pwm pairs share pwm value registers. to avoid erroneous pwm pulses, this value is buffered and will not be used by the pwm generator until the ldok bit has been set and the next pwm load cycle begins. note: when reading these registers, the value read is the buffer (not necessarily the value the pwm generator is currently using). bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bold = buffered figure 12-37. pwmx value registers high (pvalxh) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 bold = buffered figure 12-38. pwmx value registers low (pvalxl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 158 pulse-width modulator for mo tor control (pwmmc) motorola 12.9.4 pwm control register 1 pwm control register 1 (pctl1) controls pwm enabling/disabling, the loading of new modulus, prescaler, pwm values, and the pwm correction method. in addition, this register contains the softw are disable bits to force the pwm outputs to their inactive states (according to the disable mapping register). disx ? software disable bit for bank x bit this read/write bit allows the user to disable one or more pwm pins in bank x. the pins that are disabled are determi ned by the disable mapping write-once register. 1 = disable pwm pins in bank x. 0 = re-enable pwm pins at beginning of next pwm cycle. disy ? software disable bit for bank y bit this read/write bit allows the user to disable one or more pwm pins in bank y. the pins that are disabled are determi ned by the disable mapping write-once register. 1 = disable pwm pins in bank y. 0 = re-enable pwm pins at beginning of next pwm cycle. pwmint ? pwm interrupt enable bit this read/write bit allows the user to enable and disable pwm cpu interrupts. if set, a cpu interrupt will be pending when the pwmf flag is set. 1 = enable pwm cpu interrupts. 0 = disable pwm cpu interrupts. note: when pwmint is cleared, pending cpu interrupts are inhibited. pwmf ? pwm reload flag this read/write bit is set at the beginning of every reload cycle regardless of the state of the ldok bit. this bit is cleared by reading pwm control register 1 with the pwmf flag set, then writing a logi c 0 to pwmf. if another reload occurs before the clearing sequence is complete, then writing logic 0 to pwmf has no effect. 1 = new reload cycle began. 0 = new reload cycle has not begun. note: when pwmf is cleared, pending pwm cpu interrupts are cleared (not including fault interrupts). address: $0020 bit 7654321bit 0 read: disx disy pwmint pwmf isens1 isens0 ldok pwmen write: reset:00000000 figure 12-39. pwm control register 1 (pctl1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) control logic block mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 159 isens1 and isens0 ? current sense correction bits these read/write bits select the top/bottom correction scheme as shown in table 12-7 . note: the isensx bits are not buffered. changing the current sensing method can affect the present pwm cycle. ldok? load ok bit this read/write bit loads the prescaler bits of the pmctl2 register and the entire pmmodh/l and pwmvalh/l registers into a set of buffers. the buffered prescaler divisor, pwm counter modulus value, and pwm pulse will take effect at the next pwm load. set ldok by reading it when it is logic 0 and then writing a logic 1 to it. ldok is automatically cl eared after the new values are loaded or can be manually cleared before a reload by writing a 0 to it. reset clears ldok. 1 = load prescaler, modulus, and pwm values. 0 = do not load new modulus, prescaler, and pwm values. note: the user should initialize the pwm registers and set the ldok bit before enabling the pwm. a pwm cpu interrupt request can still be generated when ldok is 0. pwmen ? pwm module enable bit this read/write bit enables and disables the pwm generator and the pwm pins. when pwmen is clear, the pwm generator is disabled and the pwm pins are in the high-impedance state (unless outctl = 1). when the pwmen bit is set, the pwm generator and pwm pins are activated. for more information, see 12.7 initialization and the pwmen bit . 1 = pwm generator and pwm pins enabled 0 = pwm generator and pwm pins disabled table 12-7. correction methods current correction bits isens1 and isens0 correction method 00 01 bits ipol1, ipol2, and ip ol3 are used for correction. 10 current sensing on pins is1 , is2 , and is3 occurs during the dead-time. 11 current sensing on pins is1 , is2 , and is3 occurs at the half cycle in center-aligned mode and at the end of the cycle in edge-aligned mode. 1. the polarity of the isx pin is latched when both the top and bottom pwms are off. at the 0% and 100% duty cycle boundaries, ther e is no dead-time, so no new current value is sensed. 2. current is sensed even with 0% and 100% duty cycle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 160 pulse-width modulator for mo tor control (pwmmc) motorola 12.9.5 pwm control register 2 pwm control register 2 (pctl2) controls the pwm load frequency, the pwm correction method, and the pwm counter prescaler. for ease of software and to avoid erroneous pwm periods, some of these register bits are buffered. the pwm generator will not use the prescaler value until the ldok bit has been set, and a new pwm cycle is starting. the correcti on bits are used at the beginning of each pwm cycle (if the isensx bits are conf igured for software correction). the load frequency bits are not used until the current load cycle is complete. see figure 12-40 . note: the user should initialize this register before enabling the pwm. ldfq1 and ldfq0 ? pwm load frequency bits these buffered read/write bits select the pwm cpu load frequency according to table 12-8 . note: when reading these bits, the value read is the buffer value (not necessarily the value the pwm generator is currently using). the ldfqx bits take effect when the current load cycle is complete regardless of the state of the load okay bit, ldok. note: reading the lpfqx bit reads the buffered values and not necessarily the values currently in effect. address: $0021 bit 7654321bit 0 read: ldfq1 ldfq0 0 ipol1 ipol2 ipol3 prsc1 prsc0 write: reset:00000000 = unimplemented bold = buffered figure 12-40. pwm control register 2 (pctl2) table 12-8. pwm reload frequency reload frequency bits ldfq1 and ldfq0 pwm reload frequency 00 every pwm cycle 01 every 2 pwm cycles 10 every 4 pwm cycles 11 every 8 pwm cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) control logic block mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 161 ipol1 ? top/bottom correction bit for pwm pair 1 (pwms 1 and 2) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm value register 2. 0 = use pwm value register 1. note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). the ipolx bits take effect at the beginni ng of the next load cycle, regardless of the state of the load okay bit, ldok. ipol2 ? top/bottom correction bit for pwm pair 2 (pwms 3 and 4) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm value register 4. 0 = use pwm value register 3. note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). ipol3 ? top/bottom correction bit for pwm pair 3 (pwms 5 and 6) this buffered read/write bit selects which pwm value register is used if top/bottom correction is to be achieved without current sensing. 1 = use pwm value register 6. 0 = use pwm value register 5. note: when reading this bit, the value read is the buffer value (not necessarily the value the output control block is currently using). prsc1 and prsc0 ? pwm prescaler bits these buffered read/write bits allow the pwm clock frequency to be modified as shown in table 12-9 . note: when reading these bits, the value read is the buffer value (not necessarily the value the pwm generator is currently using). table 12-9. pwm prescaler prescaler bits prsc1 and prsc0 pwm clock frequency 00 f op 01 f op /2 10 f op /4 11 f op /8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 162 pulse-width modulator for mo tor control (pwmmc) motorola 12.9.6 dead-time write-once register the dead-time write-once register (deadtm) holds an 8-bit value which specifies the number of cpu clock cycles to us e for the dead-time when complementary pwm mode is selected. after this register is written for the first time, it cannot be rewritten unless a reset occurs. dead-time is not affected by changes to the prescaler value. 12.9.7 pwm disable mapping write-once register the pwm disable mapping write-once register (dismap) holds an 8-bit value which determines which pwm pins will be di sabled if an external fault or software disable occurs. for a further description of disable mapping, see 12.6 fault protection . after this register is written for the first time, it cannot be rewritten unless a reset occurs. 12.9.8 fault control register the fault control register (fcr) controls the fault-protection circuitry. address: $0036 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 12-41. dead-time write-once register (deadtm) address: $0037 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 12-42. pwm disable mapping write-once register (dismap) address: $0022 bit 7654321bit 0 read: fint4 fmode4 fint3 fmode3 fint2 fmode2 fint1 fmode1 write: reset:00000000 figure 12-43. fault control register (fcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) control logic block mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 163 fint4 ? fault 4 interrupt enable bit this read/write bit allows the cpu interrupt caused by faults on fault pin 4 to be enabled. the fault protection circuitry is independent of this bit and will always be active. if a fault is detected, the pwm pins will still be di sabled according to the disable mapping register. 1 = fault pin 4 will cause cpu interrupts. 0 = fault pin 4 will not cause cpu interrupts. fmode4 ? fault mode selection for fault pin 4 bit (automatic versus manual mode) this read/write bit allows the user to select between automatic and manual mode faults. for further descriptions of each mode, see 12.6 fault protection . 1 = automatic mode 0 = manual mode fint3 ? fault 3 interrupt enable bit this read/write bit allows the cpu interrupt caused by faults on fault pin 3 to be enabled. the fault protection circuitry is independent of this bit and will always be active. if a fault is detected, the pwm pins will still be di sabled according to the disable mapping register. 1 = fault pin 3 will cause cpu interrupts. 0 = fault pin 3 will not cause cpu interrupts. fmode3 ? fault mode selection for fault pin 3 bit (automatic versus manual mode) this read/write bit allows the user to select between automatic and manual mode faults. for further descriptions of each mode, see 12.6 fault protection . 1 = automatic mode 0 = manual mode fint2 ? fault 2 interrupt enable bit this read/write bit allows the cpu interrupt caused by faults on fault pin 2 to be enabled. the fault protection circuitry is independent of this bit and will always be active. if a fault is detected, the pwm pins will still be di sabled according to the disable mapping register. 1 = fault pin 2 will cause cpu interrupts. 0 = fault pin 2 will not cause cpu interrupts. fmode2 ? fault mode selection for fault pin 2 bit (automatic versus manual mode) this read/write bit allows the user to select between automatic and manual mode faults. for further descriptions of each mode, see 12.6 fault protection . 1 = automatic mode 0 = manual mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 164 pulse-width modulator for mo tor control (pwmmc) motorola fint1 ? fault 1 interrupt enable bit this read/write bit allows the cpu interrupt caused by faults on fault pin 1 to be enabled. the fault protection circuitry is independent of this bit and will always be active. if a fault is detected, the pwm pins will still be di sabled according to the disable mapping register. 1 = fault pin 1 will cause cpu interrupts. 0 = fault pin 1 will not cause cpu interrupts. fmode1 ? fault mode selection for fault pin 1 bit (automatic versus manual mode) this read/write bit allows the user to select between automatic and manual mode faults. for further descriptions of each mode, see 12.6 fault protection . 1 = automatic mode 0 = manual mode 12.9.9 fault status register the fault status register (fsr) is a read-only register that indicates the current fault status. fpin4 ? state of fault pin 4 bit this read-only bit allows the user to read the current state of fault pin 4. 1 = fault pin 4 is at logic 1. 0 = fault pin 4 is at logic 0. fflag4 ? fault event flag 4 the fflag4 event bit is set within two cpu cycles after a rising edge on fault pin 4. to clear the fflag4 bit, the user mu st write a 1 to the ftack4 bit in the fault acknowledge register. 1 = a fault has occurred on fault pin 4. 0 = no new fault on fault pin 4 fpin3 ? state of fault pin 3 bit this read-only bit allows the user to read the current state of fault pin 3. 1 = fault pin 3 is at logic 1. 0 = fault pin 3 is at logic 0. address: $0023 bit 7654321bit 0 read: fpin4 fflag4 fpin3 fflag3 fpin2 fflag2 fpin1 fflag1 write: reset:u0u0u0u0 = unimplemented u = unaffected figure 12-44. fault status register (fsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) control logic block mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 165 fflag3 ? fault event flag 3 the fflag3 event bit is set within two cpu cycles after a rising edge on fault pin 3. to clear the fflag3 bit, the user mu st write a 1 to the ftack3 bit in the fault acknowledge register. 1 = a fault has occurred on fault pin 3. 0 = no new fault on fault pin 3. fpin2 ? state of fault pin 2 bit this read-only bit allows the user to read the current state of fault pin 2. 1 = fault pin 2 is at logic 1. 0 = fault pin 2 is at logic 0. fflag2 ? fault event flag 2 the fflag2 event bit is set within two cpu cycles after a rising edge on fault pin 2. to clear the fflag2 bit, the user mu st write a 1 to the ftack2 bit in the fault acknowledge register. 1 = a fault has occurred on fault pin 2. 0 = no new fault on fault pin 2 fpin1 ? state of fault pin 1 bit this read-only bit allows the user to read the current state of fault pin 1. 1 = fault pin 1 is at logic 1. 0 = fault pin 1 is at logic 0. fflag1 ? fault event flag 1 the fflag1 event bit is set within two cpu cycles after a rising edge on fault pin 1. to clear the fflag1 bit, the user mu st write a 1 to the ftack1 bit in the fault acknowledge register. 1 = a fault has occurred on fault pin 1. 0 = no new fault on fault pin 1. 12.9.10 fault acknowledge register the fault acknowledge register (ftack) is used to acknowledge and clear the fflags. in addition, it is used to monitor the current sensing bits to test proper operation. ftack4 ? fault acknowledge 4 bit the ftack4 bit is used to acknowledge a nd clear fflag4. this bit will always read 0. writing a 1 to this bit will clea r fflag4. writing a 0 will have no effect. address: $0024 bit 7654321bit 0 read: 0 0 dt6 dt5 dt4 dt3 dt2 dt1 write: ftack4 ftack3 ftack2 ftack1 reset:00000000 = unimplemented figure 12-45. fault acknowledge register (ftack) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 166 pulse-width modulator for mo tor control (pwmmc) motorola ftack3 ? fault acknowledge 3 bit the ftack3 bit is used to acknowledge a nd clear fflag3. this bit will always read 0. writing a 1 to this bit will clea r fflag3. writing a 0 will have no effect. ftack2 ? fault acknowledge 2 bit the ftack2 bit is used to acknowledge a nd clear fflag2. this bit will always read 0. writing a 1 to this bit will clea r fflag2. writing a 0 will have no effect. ftack1 ? fault acknowledge 1 bit the ftack1 bit is used to acknowledge a nd clear fflag1. this bit will always read 0. writing a 1 to this bit will clea r fflag1. writing a 0 will have no effect. dt6 ? dead-time 6 bit current sensing pin is3 is monitored immediately before dead-time ends due to the assertion of pwm6. dt5 ? dead-time 5 bit current sensing pin is3 is monitored immediately before dead-time ends due to the assertion of pwm5. dt4 ? dead-time 4 bit current sensing pin is2 is monitored immediately before dead-time ends due to the assertion of pwm4. dt3 ? dead-time 3 bit current sensing pin is2 is monitored immediately before dead-time ends due to the assertion of pwm3. dt2 ? dead-time 2 bit current sensing pin is1 is monitored immediately before dead-time ends due to the assertion of pwm2. dt1 ? dead-time 1 bit current sensing pin is1 is monitored immediately before dead-time ends due to the assertion of pwm1. 12.9.11 pwm output control register the pwm output control register (pwmout) is used to manually control the pwm pins. address: $0025 bit 7654321bit 0 read: 0 outctl out6 out5 out4 out3 out2 out1 write: reset:00000000 = unimplemented figure 12-46. pwm output control register (pwmout) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator for motor control (pwmmc) pwm glossary mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola pulse-width modulator for motor control (pwmmc) 167 outctl? output control enable bit this read/write bit allows the user to manually control the pwm pins. when set, the pwm generator is no longer the input to the dead-time and output circuitry. the outx bits determine the state of the pwm pins. setting the outctl bit does not disable the pwm generator. the generator continues to run, but is no longer the input to the pwm dead-time and output circuitry. when outctl is cleared, the outputs of the pwm generator immediately become the inputs to the dead-time and output circuitry. 1 = pwm outputs controlled manually 0 = pwm outputs determined by pwm generator out6?out1? pwm pin output control bits these read/write bits control the pwm pins according to table 12-10 . 12.10 pwm glossary cpu cycle ? one internal bus cycle (1/f op ) pwm clock cycle (or period) ? one tick of the pwm counter (1/f op with no prescaler). see figure 12-47 . pwm cycle (or period) center-aligned mode: the time it takes the pwm counter to count up and count down (modulus * 2/f op assuming no prescaler). see figure 12-47 . edge-aligned mode: the time it takes the pwm counter to count up (modulus/f op ). see figure 12-47 . table 12-10. outx bits outx bit complementary mode independent mode out1 1 ? pwm1 is active. 0 ? pwm1 is inactive. 1 ? pwm1 is active. 0 ? pwm1 is inactive. out2 1 ? pwm2 is complement of pwm 1. 0 ? pwm2 is inactive. 1 ? pwm2 is active. 0 ? pwm2 is inactive. out3 1 ? pwm3 is active. 0 ? pwm3 is inactive. 1 ? pwm3 is active. 0 ? pwm3 is inactive. out4 1 ? pwm4 is complement of pwm 3. 0 ? pwm4 is inactive. 1 ? pwm4 is active. 0 ? pwm4 is inactive. out5 1 ? pwm5 is active. 0 ? pwm5 is inactive. 1 ? pwm5 is active. 0 ? pwm5 is inactive. out6 1 ? pwm 6 is complement of pwm 5. 0 ? pwm6 is inactive. 1 ? pwm6 is active. 0 ? pwm6 is inactive. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse-width modulator fo r motor control (pwmmc) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 168 pulse-width modulator for mo tor control (pwmmc) motorola figure 12-47. pwm clock cycle and pwm cycle definitions pwm load frequency ? frequency at which new pwm parameters get loaded into the pwm. see figure 12-48 . figure 12-48. pwm load cycle/frequency definition pwm clock cycle pwm cycle (or period) pwm pwm cycle (or period) center-aligned mode edge-aligned mode clock cycle reload new modulus, prescaler, & pwm values if ldok = 1 reload new modulus, prescaler, & pwm values if ldok = 1 pwm load cycle ldfq1:ldfq0 = 01 ? reload every two cycles (1/pwm load frequency) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 169 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 13. serial communicat ions interface module (sci) 13.1 introduction this section describes the serial communications interface module (sci, version d), which allows high-speed asynchronous communications with peripheral devices and other microcontroller units (mcus). 13.2 features features of the sci module include: full-duplex operation standard mark/space non-return-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests separate receiver and transmitter programmable transmitter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 170 serial communications interface module (sci) motorola serial communications interface module (sci) figure 13-1. block diagram highlighting sci block and pins clock generator module system integration module serial communications interface module serial peripheral interface module (2) timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 112 bytes user flash ? 32,256 bytes user ram ? 768 bytes monitor rom ? 240 bytes user flash vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq v ss v dd v ddad pta7?pta0 pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b (1) pte1/tch0b (1) pte0/tclkb (1) ptf5/txd ptf4/rxd ptf3/miso (1) ptf2/mosi (1) ptf1/ss (1) ptf0/spsck (1) timer interface module b pulse-width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9(1) ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssad v dda v ssa (3) pwmgnd v refl (3) v refh notes: 1. these pins are not avail able in the 56-pin sdip package. 2. this module is not avail able in the 56-pin sdip package. 3. in the 56-pin sdip package, these pins are bonded together. single break module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 171 13.3 functional description figure 13-2 shows the structure of the sci module. the sci allows full-duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. figure 13-2. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci ptf4/rxd ptf5/txd internal bus txinv loops 4 16 pre- scaler baud rate generator f op f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 172 serial communications interface module (sci) motorola 13.3.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 13-4 . figure 13-4. sci data formats addr. register name bit 7654321bit 0 $0038 sci control register 1 (scc1) see page 183. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0039 sci control register 2 (scc2) see page 185. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $003a sci control register 3 (scc3) see page 187. read: r8 t8 00 orie neie feie peie write: r r r reset:uu000000 $003b sci status register 1 (scs1) see page 188. read: scte tc scrf idle or nf fe pe write:rrrrrrrr reset:11000000 $003c sci status register 2 (scs2) see page 191. read:000000bkfrpf write:rrrrrrrr reset:00000000 $003d sci data register (scdr) see page 192. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $003e sci baud rate register (scbr) see page 192. read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: r r r reset:00000000 r = reserved u = unaffected figure 13-3. sci i/o register summary bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 possible parity bit possible parity bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 173 13.3.2 transmitter figure 13-5 shows the structure of the sci transmitter. figure 13-5. sci transmitter pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc f op parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register tc sctie tcie scte m ensci loops te ptf5/txd txinv internal bus 4 pre- scaler scp1 scp0 scr1 scr2 scr0 baud divider 16 transmitter cpu interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 174 serial communications interface module (sci) motorola 13.3.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 13.3.2.2 character transmission during an sci transmission, the transmit shi ft register shifts a character out to the ptf5/txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift r egister. to initiate an sci transmission: 1. enable the sci by writing a 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the transmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitte r control logic automatically loads the transmit shift register with a preamble of 1s. after the preamble shifts out, control logic transfers the scdr data into th e transmit shift register. a 0 start bit automatically goes into the l east significant bit (lsb) position of the transmit shift register. a 1 stop bit goes into the most significant bit (msb) position. the sci transmitter empty bit, scte, in scs1 becomes set when the scdr transfers a byte to the transmit shift register. the scte bit indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the ptf5/txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitte r and receiver relinquish control of the port e pins. 13.3.2.3 break characters writing a 1 to the send break bit, sbk, in sc c2 loads the transmit shift register with a break character. a break character contains all 0s and has no start, stop, or parity bit. break character length de pends on the m bit in scc1. as long as sbk is at 1, transmitter logic conti nuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift re gister finishes transmitting the last break character and then transmits at l east one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 175 the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception-in-progress flag (rpf) bits 13.3.2.4 idle characters an idle character contains all 1s and has no start, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmissi on, the ptf5/txd pin becomes idle after completion of the transmission in progre ss. clearing and then setting the te bit during a transmission queues an idle charac ter to be sent after the character currently being transmitted. note: when a break sequence is followed immediat ely by an idle character, this sci design exhibits a condition in which the break character length is reduced by one half bit time. in this instance, the break sequence will consist of a valid start bit, eight or nine data bits (as defined by the m bit in scc1) of logic 0 and one half data bit length of logic 0 in the stop bit position followed immediately by the idle character. to ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress. when queueing an idle character, return the te bit to 1 before the stop bit of the current character shifts out to the ptf5 /txd pin. setting te after the stop bit appears on ptf5/txd causes data previous ly written to the scdr to be lost. a good time to toggle the te bit is w hen the scte bit becomes set and just before writing the next byte to the scdr. 13.3.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control register 1 (scc1) reverses the polarity of transmitted data. all transm itted values, including idle, break, start, and stop bits, are inverted when txinv is at 1. see 13.7.1 sci control register 1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 176 serial communications interface module (sci) motorola 13.3.2.6 transmitter interrupts these conditions can generate cpu interr upt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to t he transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the tr ansmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 13.3.3 receiver figure 13-6 shows the structure of the sci receiver. 13.3.3.1 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 13.3.3.2 character reception during an sci reception, the receive shift register shifts char acters in from the ptf4/rxd pin. the sci data register (s cdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to th e scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. 13.3.3.3 data sampling the receiver samples the ptf4/rxd pin at the rt clock rate. the rt clock is an internal signal with a fr equency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at these times (see figure 13-7 ): after every start bit after the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at rt8, rt9, and rt10 return a valid 1 and the majority of the next rt8, rt9, and rt10 samples return a valid 0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 177 figure 13-6. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request cpu interrupt request sci data register r8 orie neie feie peie scrie ilie rwu scrf idle or nf fe pe ptf4/rxd internal bus pre- scaler baud divider 4 16 scp1 scp0 scr1 scr2 scr0 f op f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 178 serial communications interface module (sci) motorola figure 13-7. receiver data sampling to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 13-1 summarizes the results of the start bit verification samples. if start bit verification is no t successful, the rt clock is reset and a new search for a start bit begins. rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb ptf4/rxd table 13-1. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 179 to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 13-2 summarizes the results of the data bit samples. note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are 1s following a successful start bit verification, the noise flag (nf) is set and t he receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 13-3 summarizes the results of the stop bit samples. table 13-2. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 13-3. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 180 serial communications interface module (sci) motorola 13.3.3.4 framing errors if the data recovery logic does not detect a 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. the fe flag is set at the same time that the scrf bit is set. a break character that has no stop bit also sets the fe bit. 13.3.3.5 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bit in scc1, either of tw o conditions on the ptf4/rxd pin can bring the receiver out of the standby state: address mark ? an address mark is a 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes the receiver from the standby state by clearing the rwu bit. the address mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the ptf4/rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. note: clearing the wake bit after the ptf4/rxd pin has been idle can cause the receiver to wake up immediately. 13.3.3.6 receiver interrupts these sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a char acter to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in sc s1 indicates that 10 or 11 consecutive 1s shifted in from the ptf4/rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) wait mode mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 181 13.3.3.7 error interrupts these receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate sci error cpu interrupt requests. 13.4 wait mode the wait and stop instructions put the mcu in low power-consumption standby modes. the sci module remains active after the execution of a wait instruction. in wait mode the sci module registers are not accessible by the cpu. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not requir ed during wait mode, reduce power consumption by disabling the module bef ore executing the wait instruction. 13.5 sci during bre ak module interrupts the system integration module (sim) contro ls whether status bits in other modules can be cleared during interrupts generated by the break module. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break interrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 182 serial communications interface module (sci) motorola 13.6 i/o signals port f shares two of its pins with the sci module. the two sci input/output (i/o) pins are: ptf5/txd ? transmit data ptf4/rxd ? receive data 13.6.1 ptf5/txd (transmit data) the ptf5/txd pin is the serial data ou tput from the sci transmitter. the sci shares the ptf5/txd pin with port f. when the sci is enabled, the ptf5/txd pin is an output regardless of the state of the ddrf5 bit in data direction register f (ddrf). 13.6.2 ptf4/rxd (receive data) the ptf4/rxd pin is the serial data inpu t to the sci receiver. the sci shares the ptf4/rxd pin with port f. when the sci is enabled, the ptf4/rxd pin is an input regardless of the state of the ddrf4 bit in data direction register f (ddrf). 13.7 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 13.7.1 sci control register 1 sci control register 1 (scc1): enables loop-mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 183 loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the ptf4/rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note: setting the txinv bit inverts all transmitted values, incl uding idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit determines whether sci characters are eight or nine bits long. see table 13-4 . the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit determines which co ndition wakes up the sci: a 1 (address mark) in the most significant bit (msb) po sition of a received character or an idle condition on the ptf4/rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup address: $0038 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 13-8. sci control register 1 (scc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 184 serial communications interface module (sci) motorola ilty ? idle line type bit this read/write bit determines when the sci starts counting 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognitio n, but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit. 0 = idle character bit count begins after start bit. pen ? parity enable bit this read/write bit enables the sci parity function. see table 13-4 . when enabled, the parity function inserts a parity bit in the most significant bit position. see figure 13-4 . reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity. see table 13-4 . reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. table 13-4. character format selection control bits character format m pen:pty start bits data bits parity stop bits character length 0 0x 1 8none1 10 bits 1 0x 1 9none1 11 bits 0 10 1 7even1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8even1 11 bits 1 11 1 8 odd 1 11 bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 185 13.7.2 sci control register 2 sci control register 2 (scc2): enables these cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. setting the sctie bit in scc3 enables scte cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. setting the scrie bit in scc3 enables the scrf bit to generate cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests address: $0039 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 13-9. sci control register 2 (scc2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 186 serial communications interface module (sci) motorola te ? transmitter enable bit setting this read/write bit begins the tr ansmission by sending a preamble of 10 or 11 1s from the transmit shift regist er to the ptf5/txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the ptf5/txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an idle charac ter to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note: writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines w hether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/write bit transmits a break character followed by a 1. the 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no 1s between them . reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note: do not toggle the sbk bit immediately afte r setting the scte bit. toggling sbk too early causes the sci to send a break character instead of a preamble. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 187 13.7.3 sci control register 3 sci control register 3 (scc3): stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables sci receiver full (scrf) enables sci transmitter empty (scte) enables the following interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts ? parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other eight bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is load ed into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled address: $003a bit 7654321bit 0 read: r8 t8 00 orie neie feie peie write: r r r reset:uu000000 r = reserved u = unaffected figure 13-10. sci control register 3 (scc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 188 serial communications interface module (sci) motorola feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. see 13.7.4 sci status register 1 . reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt r equests from pe bit disabled 13.7.4 sci status register 1 sci status register 1 (scs1) contai ns flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift r egister data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmitter empty bit this clearable, read-only bit is set w hen the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $003b bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write:rrrrrrrr reset:11000000 r= reserved figure 13-11. sci status register 1 (scs1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 189 tc ? transmission complete bit this read-only bit is set when the scte bit is set and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble, or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set, scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active or idle since the idle bit was cleared or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an overrun to occur between reads of scs1 and scdr in the flag-clearing sequence. figure 13-12 shows the normal flag-clearing sequence and an example of an overr un caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-cl earing sequence reads byte 3 in the scdr instead of byte 2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 190 serial communications interface module (sci) motorola figure 13-12. flag clearing sequence in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the ptf4/rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 191 13.7.5 sci status register 2 sci status register 2 (scs2) contai ns flags to signal these conditions: break character detected incoming data bkf ? break flag this clearable, read-only bit is set when the sci detects a break character on the ptf4/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after logic 1s again appear on the ptf4/rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ?reception-in-progress flag this read-only bit is set when the receiv er detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch, or when the receiver det ects an idle character. polling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $003c bit 7654321bit 0 read:000000bkfrpf write:rrrrrrrr reset:00000000 r= reserved figure 13-13. sci status register 2 (scs2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 192 serial communications interface module (sci) motorola 13.7.6 sci data register the sci data register (scdr) is the bu ffer between the internal data bus and the receive and transmit shift registers. rese t has no effect on data in the sci data register. r7/t7:r0/t0 ? receive/transmit data bits reading address $003d accesses the re ad-only received data bits, r7:r0. writing to address $003d writes the data to be transmitted, t7:t0. reset has no effect on the sci data register. 13.7.7 sci baud rate register the baud rate register (scbr) selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 13-5 . reset clears scp1 and scp0. address: $003d bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 13-14. sci data register (scdr) address: $003e bit 7654321bit 0 read: 0 0 scp1 scp0 0 scr2 scr1 scr0 write: r r r reset:00000000 r = reserved figure 13-15. sci baud rate register (scbr) table 13-5. sci baud rate prescaling scp1:scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial communications interface module (sci) 193 scr2?scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 13-6 . reset clears scr2?scr0. use this formula to calculate the sci baud rate: where: f op = internal operating frequency pd = prescaler divisor bd = baud rate divisor table 13-7 shows the sci baud rates that can be generated with a 4.9152-mhz crystal with the cgm set for an f op of 7.3728 mhz and the cgm set for an f op of 4.9152 mhz. table 13-6. sci baud rate selection scr2:scr1:scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate f op 64 pd bd ------------------------------------ = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface module (sci) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 194 serial communications interface module (sci) motorola table 13-7. sci baud rate selection examples scp1:scp0 prescaler divisor (pd) scr2:scr1:scr0 baud rate divisor (bd) baud rate (f op = 7.3728 mhz) baud rate (f op = 4.9152 mhz) 00 1 000 1 115,200 76,800 00 1 001 2 57,600 38,400 00 1 010 4 28,800 19,200 00 1 011 8 14,400 9600 00 1 100 16 7200 4800 00 1 101 32 3600 2400 00 1 110 64 1800 1200 00 1 111 128 900 600 01 3 000 1 38,400 25,600 01 3 001 2 19,200 12,800 01 3 010 4 9600 6400 01 3 011 8 4800 3200 01 3 100 16 2400 1600 01 3 101 32 1200 800 01 3 110 64 600 400 01 3 111 128 300 200 10 4 000 1 28,800 19,200 10 4 001 2 14,400 9600 10 4 010 4 7200 4800 10 4 011 8 3600 2400 10 4 100 16 1800 1200 10 4 101 32 900 600 10 4 110 64 450 300 10 4 111 128 225 150 11 13 000 1 8861.5 5907.7 11 13 001 2 4430.7 2953.8 11 13 010 4 2215.4 1476.9 11 13 011 8 1107.7 738.5 11 13 100 16 553.8 369.2 11 13 101 32 276.9 184.6 11 13 110 64 138.5 92.3 11 13 111 128 69.2 46.2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola system integr ation module (sim) 195 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 14. system inte gration module (sim) 14.1 introduction this section describes the system integration module (sim). together with the central processor unit (cpu), the sim c ontrols all microcontroller unit (mcu) activities. a block diagram of the sim is shown in figure 14-1 . the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals: ? wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources table 14-1 shows the internal signal names used in this section. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 196 system integration module (sim) motorola figure 14-1. sim block diagram wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module wait cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2 table 14-1. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk phase-locked loop (pll) circuit output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim bus clock control and generation mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola system integr ation module (sim) 197 14.2 sim bus clock co ntrol and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are gener ated from an incoming clock, cgmout, as shown in figure 14-2 . this clock can come from either an external oscillator or from the on-chip phase-locked loop (pll) circuit. see section 4. clock generator module (cgm) . figure 14-2. cgm clock signals 14.2.1 bus timing in user mode , the internal bus frequency is eith er the crystal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. see section 4. clock generator module (cgm) . 14.2.2 clock startup from por or lvi reset when the power-on reset (por) module or the low-voltage inhibit (lvi) module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 cgmxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the internal bus (ibus) clocks star t upon completion of the timeout. 14.2.3 clocks in wait mode in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wa it mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. pll osc1 cgmxclk 2 bus clock generators sim cgm sim counter ptc2 monitor mode clock select circuit cgmvclk bcs 2 a b s* cgmout *when s = 1, cgmout = b user mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 198 system integration module (sim) motorola 14.3 reset and syst em initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly (cop) module low-voltage inhibit (lvi) module illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 14.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). see 14.7.2 sim reset status register . 14.3.1 external pin reset pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 14-2 for details. figure 14-3 shows the relative timing. figure 14-3. external reset timing table 14-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola system integr ation module (sim) 199 14.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal reset signal (irst) continues to be asserted for an additional 32 cycles (see figure 14-5 ). an internal reset can be caused by an illegal address, illegal opcode, cop timeout, lvi, or por. (see figure 14-4 .) figure 14-4. sources of internal reset note: for lvi or por resets, the sim cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal re set signal then follows the sequence from the falling edge of rst , as shown in figure 14-5 . figure 14-5. internal reset timing the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 14.3.2.1 powe r-on reset (por) when power is first applied to the mcu, the power-on reset (por) module generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. illegal address rst illegal opcode rst coprst lvi por internal reset irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 200 system integration module (sim) motorola figure 14-6. por recovery at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables cgmout. internal clocks to the cpu and modules are held inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. 14.3.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, write any value to location $ffff. writing to location $ffff clears the cop counter and bi ts 12?4 of the sim counter. the sim counter output, which occurs at least every 2 13 ?2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v hi while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim counter mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola system integr ation module (sim) 201 pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v hi on the rst pin disables the cop module. 14.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. because the mc68hc908mr32 has stop mode disabled, execution of the stop instruction will cause an illegal opcode reset. 14.3.2.4 illegal address reset an opcode fetch from addresses other than flash or ram addresses generates an illegal address reset (unimplemented locations within memory map). the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. 14.3.2.5 forced monitor mode entry reset (menrst) the menrst module monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($ff). when the mcu comes out of reset, it is forced into monitor mode. 14.3.2.6 low-voltage inhibit (lvi) reset the low-voltage inhibit (lvi) module asserts its output to the sim when the v dd voltage falls to the v lvrx voltage and remains at or below that level for at least nine consecutive cpu cycles (see 19.5 dc electrical characteristics ). the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cgmxclk cycles later, the cpu is releas ed from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 14.4 sim counter the sim counter is used by the power-on reset (por) module to allow the oscillator time to stabilize before enabling the inte rnal bus (ibus) clocks. the sim counter also serves as a prescaler for the com puter operating properly (cop) module. the sim counter overflow supplies the clock for the cop module. the sim counter is 13 bits long and is clocked by the falling edge of cgmxclk. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 202 system integration module (sim) motorola 14.4.1 sim counter during power-on reset the power-on reset (por) module detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the clock generation (cgm) module to drive the bus clock state machine. 14.4.2 sim counter and reset states external reset has no effect on the sim counter. the sim counter is free-running after all reset states. for counter control and internal reset recovery sequences, see 14.3.2 active resets from internal sources . 14.5 exception control normal, sequential program execution can be changed in three different ways: 1. interrupts: a. maskable hardware cpu interrupts b. non-maskable software interrupt instruction (swi) 2. reset 3. break interrupts 14.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the return-from-interrupt (rti) instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 14-7 shows interrupt entry timing. figure 14-9 shows interrupt recovery timing. figure 14-7 . interrupt entry module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit start addr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola system integr ation module (sim) 203 interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). see figure 14-8 . figure 14-8. interrupt processing no no yes as many interrupts as exist on chip swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes no yes no no yes i bit set? from reset break or swi i bit set? interrupt? yes interrupt? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 204 system integration module (sim) motorola figure 14-9. interrupt recovery 14.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the si m checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 14-10 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the load-accumulator-from- memory (lda) instruction is executed. figure 14-10 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power mode mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola system integr ation module (sim) 205 register or uses the indexed addressing m ode, software should save the h register and then restore it prior to exiting the routine. 14.5.1.2 software interrupt (swi) instruction the software interrupt (swi) instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. 14.5.2 reset all reset sources always have equal and highest priority and cannot be arbitrated. 14.6 low-power mode executing the wait instruction puts the mcu in a low power-consumption mode for standby situations. the sim holds the cpu in a non-clocked state. wait clears the interrupt mask (i) in the condition c ode register, allowing interrupts to occur. 14.6.1 wait mode in wait mode, the cpu clocks are inacti ve while the peripheral clocks continue to run. figure 14-11 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset. if the cop disable bit, copd, in the configuration register is logic 0, th en the computer operating properly module (cop) is enabled and remains active in wait mode. figure 14-11. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 206 system integration module (sim) motorola figure 14-12 and figure 14-13 show the timing for wait recovery. figure 14-12. wait recovery from interrupt figure 14-13. wait recovery from internal reset 14.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is hard wired at the normal delay of 4096 cgmxclk cycles. it is important to note that when using the pwm generator, its outputs will stop toggling when stop mode is entered. the pwm module must be disabled before entering stop mode to prevent external inverter failure. 14.7 sim registers this subsection descri bes the sim registers. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola system integr ation module (sim) 207 14.7.1 sim break status register the sim break status register (sbsr) cont ains a flag to indicate that a break caused an exit from wait mode. sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. reset clears sbsw. 1 = wait mode was exited by break interrupt. 0 = wait mode was not exited by break interrupt. sbsw can be read within the break state sw i routine. the user can modify the return address on the stack by subtracting one from it. 14.7.2 sim reset status register the sim reset status register (srsr) contains six flags that show the source of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r= reserved note 1. writing a logic 0 clears sbsw. figure 14-14. sim break status register (sbsr) address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad menrst lvi 0 write:rrrrrrrr reset:10000000 r= reserved figure 14-15. sim reset status register (srsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 208 system integration module (sim) motorola cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr menrst ? forced monitor mode entry reset bit 1 = last reset caused by the menrst circuit 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr 14.7.3 sim break flag control register the sim break control register (sbfcr) c ontains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 14-16. sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 209 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 15. serial peripheral interface module (spi) 15.1 introduction the serial peripheral interface (spi) modul e allows full-duplex, synchronous, serial communications with peripheral devices. 15.2 features features of the spi module include: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts with central processor unit (cpu) service: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag with cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated circuit) compatibility f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 210 serial peripheral interface module (spi) motorola serial peripheral in terface module (spi) figure 15-1. block diagram highlighting spi block and pins clock generator module system integration module serial communications interface module serial peripheral interface module (2) timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 112 bytes user flash ? 32,256 bytes user ram ? 768 bytes monitor rom ? 240 bytes user flash vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq v ss v dd v ddad pta7?pta0 pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b (1) pte1/tch0b (1) pte0/tclkb (1) ptf5/txd ptf4/rxd ptf3/miso (1) ptf2/mosi (1) ptf1/ss (1) ptf0/spsck (1) timer interface module b pulse-width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9(1) ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssad v dda v ssa (3) pwmgnd v refl (3) v refh notes: 1. these pins are not available in the 56-pin sdip package. 2. this module is not avail able in the 56-pin sdip package. 3. in the 56-pin sdip package, these pins are bonded together. single break module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) pin name conventions mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 211 15.3 pin name conventions the generic names of the spi input/output (i/o) pins are: ss , slave select spsck, spi serial clock mosi, master out/slave in miso, master in/slave out spi pins are shared by parallel i/o ports or have alternate functions. the full name of an spi pin reflects the name of the shared port pin or the name of an alternate pin function. the generic pin names appear in the text that follows. table 15-1 shows the full names of the spi i/o pins. 15.4 functional description figure 15-3 shows the structure of the spi module and figure 15-2 shows the locations and contents of the spi i/o registers. the spi module allows full-duplex, sy nchronous, serial communication between the microcontroller unit (mcu) and per ipheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt-driven. all spi interrupts can be serviced by the cpu. table 15-1. pin name conventions generic pin names: miso mosi spsck ss full pin names: ptf3/miso ptf2/mosi ptf0/spsck ptf1/ss addr. register name bit 7 6 5 4 3 2 1 bit 0 $0044 spi control register (spcr) see page 228. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0045 spi status and control register (spscr) see page 229. read: sprf errie ovrf modf spte modfen spr1 spr0 write: r r r r reset:00001000 $0046 spi data register (spdr) see page 232. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset r= reserved figure 15-2. spi i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 212 serial peripheral interface module (spi) motorola figure 15-3. spi module block diagram transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 cgmout 2 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus (from sim) modfen errie control modf spmstr mosi miso spsck ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 213 15.4.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note: configure the spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. see 15.12.1 spi control register . only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the spi data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the by te begins shifting out on the mosi pin under the control of the serial clock. see figure 15-4 . figure 15-4. full-duplex master-slave connections the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. see 15.12.2 spi status and control register . through the spsck pin, the baud-rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. writing to the spi data register clears the spte bit. 15.4.2 slave mode the spi operates in slave mode when the spmstr bit is clear. in slave mode the spsck pin is the input for the serial cloc k from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low until the transmission is complete. see 15.6.2 mode fault error . shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 214 serial peripheral interface module (spi) motorola in a slave spi module, data enters the shift register under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. the maximum frequency of the spsck for an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock that can be generated). the frequen cy of the spsck for an spi co nfigured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the sl ave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its transmit data register at leas t one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the sl ave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see 15.5 transmission formats . note: if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 15.5 transmission formats during an spi transmission, data is simu ltaneously transmitted (shifted out serially) and received (shifted in serially). a seri al clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selecti on of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple-master bus contention. 15.5.1 clock phase and polarity controls software can select any of four combinations of serial clock (spsck) phase and polarity using two bits in the spi contro l register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no significant effect on the transmission format. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) transmission formats mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 215 the clock phase (cpha) control bit select s one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmi ssions to allow a master device to communicate with peripheral slav es having different requirements. note: before writing to the cpol bit or the cp ha bit, disable the spi by clearing the spi enable bit (spe). 15.5.2 transmission format when cpha = 0 figure 15-5 shows an spi transmission in which cp ha is logic 0. the figure should not be used as a replacement for data sheet parametric information.two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a mast er or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the ma ster and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 15.6.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slave?s ss pin must be toggled back to high and then low again bet ween each byte transmitted as shown in figure 15-6 . figure 15-5. transmission format (cpha = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck, cpol = 0 spsck, cpol = 1 mosi from master miso from slave ss , to slave capture strobe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 216 serial peripheral interface module (spi) motorola figure 15-6. cpha/ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmi t data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. 15.5.3 transmission format when cpha = 1 figure 15-7 shows an spi transmission in which cp ha is logic 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a mast er or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the ma ster and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. see 15.6.2 mode fault error . when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first spsc k edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the tr ansmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift regist er after the current transmission. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 217 figure 15-7. transmission format (cpha = 1) 15.5.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr starts a transmission. cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycle begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (sel ected by spr1:spr0) affects the delay from the write to spdr and the start of the spi transmission. see figure 15-8 the internal spi clock in the master is a free-running derivative of the internal mcu clock. to c onserve power, it is enabl ed only when both the spe and spmstr bits are set. spsck edges occur halfway through the low time of the internal mcu clock. since the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to th e slower spsck. this uncertainty causes the variation in the initiation delay shown in figure 15-8 . this delay is no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. 15.6 error conditions these flags signal sp i error conditions: overflow (ovrf) ? failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (modf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck, cpol = 0 spsck, cpol = 1 mosi from master miso from slave ss , to slave capture strobe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 218 serial peripheral interface module (spi) motorola figure 15-8. transmission start delay (master) 15.6.1 overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = internal clock 2; earliest latest 2 possible start points spsck = internal clock 8; 8 possible start points earliest latest spsck = internal clock 32; 32 possible start points earliest latest spsck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock initiation delay from write spdr to transfer begin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 219 an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. modf and ovrf can generate a receiver/error cpu interrupt request. see figure 15-11 . it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if the cpu sprf interrupt is enabled and the ovrf interrupt is not, watch for an overflow condition. figure 15-9 shows how it is possible to miss an overflow. the first part of figure 15-9 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit can be set in between the time that spscr and spdr are read. figure 15-9. missed read of overflow condition in this case, an overflow can easily be missed. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spsc r following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 15-10 illustrates this process. generally, to avoid this second spscr read, enable the ovrf interrupt to the cpu by setting the errie bit. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 220 serial peripheral interface module (spi) motorola figure 15-10. clearing sprf when ovrf interrupt is not enabled 15.6.2 mode fault error setting the spmstr bit selects master mode and configur es the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr selects slave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to t he mcu, a mode fault error occurs if: the ss pin of a slave spi goes high during a transmission. the ss pin of a master spi goes low at any time. for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. modf and ovrf can generate a receiver/error cpu interrupt request. see figure 15-11 . it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) error conditions mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 221 in a master spi with the mode fault enable bit (modfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a mode fault in a master spi causes these events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. note: to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction regist er of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the trans mission continues until the spsck returns to its idle level followin g the shift of the last data bit. see 15.5 transmission formats . note: setting the modf flag does not clear the spmstr bit. reading spmstr when modf = 1 will indicate a mode fault error occurred in either master mode or slave mode. when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no spsck is sent to that slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or reset the spi in any way. software can abort the spi trans mission by clearing the spe bit of the slave. note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the sl ave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr wi th the modf bit set and then write to the spcr register. this entire clearing procedure must occur with no modf condition existing or else the flag is not cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 222 serial peripheral interface module (spi) motorola 15.7 interrupts four spi status flags can be enabled to generate cpu interrupt requests as shown in table 15-2 . the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests, provided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt requests, provi ded that the spi is enabled (spe = 1). (see figure 15-11 .) figure 15-11. spi interrupt request generation the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error cpu interrupt requests. table 15-2. spi interrupts flag request spte transmitter empty spi transmitter cp u interrupt request (sptie = 1, spe = 1) sprf receiver full spi receiver cpu interrupt request (sprie = 1) ovrf overflow spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1) spte sptie sprf sprie errie modf ovrf spe spi transmitter cpu interrupt request spi receiver/error cpu interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) resetting the spi mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 223 these sources in the spi status and control register can generate cpu interrupt requests: spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf can generate either an spi receiver/error or cpu interrupt. spi transmitter empty (spte) ? t he spte bit becomes set every time a byte transfers from the transmit data re gister to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte can generate either an spte or cpu interrupt request. 15.8 resetting the spi any system reset completely resets the sp i. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logic is defaul ted back to being general-purpose i/o. these items are reset only by a system reset: all control bits in the spcr all control bits in the spscr (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions without having to set all co ntrol bits again when spe is set back high for the next transmission. by not resetting the sprf, ovrf, and modf fl ags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabl ed by a mode fault occurring in an spi that was configured as a master with the modfen bit set. 15.9 queuing transmission data the double-buffered transmit data regist er allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates w hen the transmit data buffer is ready to accept new data. write to the transmit data register only when the spte bit is high. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 224 serial peripheral interface module (spi) motorola figure 15-12 shows the timing associated with doing back-to-back transmissions with the spi (spsck has cpha:cpol = 1:0). figure 15-12. sprf/spte cpu interrupt timing for a slave, the transmit data buffer allo ws back-to-back trans missions without the slave precisely timing its writes between trans missions as in a system with a single data buffer. also, if no new data is wr itten to the data buffer, the last value contained in the shift register is the next data word to be transmitted. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus c ycles after the transmit buffer empties into the shift register. this allows the us er to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. 15.10 low-power mode the wait instruction puts the mcu in a low power-consumption standby mode. the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are not ac cessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msbbit 6 bit 5 bit 4 bit 2 bit 1 lsbmsbbit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsbmsbbit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. cpha:cpol = 1:0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o signals mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 225 if spi module functions are not requi red during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow c ondition occurs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). see 15.7 interrupts . since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 15.11 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. the pins are: miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becomes an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 15.11.1 miso (master in/slave out) miso is one of the two spi module pins that transmits serial data. in full duplex operation, the miso pin of the master sp i module is connected to the miso pin of the slave spi module. the master spi si multaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enab led only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple-slave system, a logic 1 on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direct ion of the miso pin regardless of the state of the data direction register of the shared i/o port. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 226 serial peripheral interface module (spi) motorola 15.11.2 mosi (master out/slave in) mosi is one of the two spi module pins t hat transmits serial data. in full-duplex operation, the mosi pin of the master sp i module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direct ion of the mosi pin regardless of the state of the data direction register of the shared i/o port. 15.11.3 spsck (serial clock) the serial clock synchronizes data tr ansmission between master and slave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the clock input. in full-duplex oper ation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi controls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 15.11.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the star t of a transmission. see 15.5 transmission formats . since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted fo r the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 15-13 . figure 15-13. cpha/ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. see 15.12.2 spi status and control register . note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignor es all incoming spsck clocks, even if it was already in the middle of a transmission. when an spi is configured as a master, the ss input can be used in conjunction with the modf flag to prevent multiple masters from driving mosi and spsck. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 227 (see 15.6.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shar ed i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the port data register. see table 15-3 . 15.11.5 v ss (clock ground) v ss is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. to reduce the ground return path loop and minimize radio frequency (rf) emissions, connect the ground pin of the slave to the v ss pin of the master. 15.12 i/o registers three registers control and monitor spi operation: spi control register, spcr spi status and control register, spscr spi data register, spdr 15.12.1 spi control register the spi control register (spcr): enables spi module interrupt requests selects cpu interrupt requests or dma service requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module table 15-3. spi configuration spe spmstr modfen spi conf iguration state of ss logic 0 x (1) 1. x = don?t care x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 11 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 228 serial peripheral interface module (spi) motorola sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic state of the spsck pin between transmissions. see figure 15-5 and figure 15-7 . to transmit data between spi modules, the spi modules must have identical cpol values. reset clears the cpol bit. cpha ? clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. see figure 15-5 and figure 15-7 . to transmit data between spi modules, the spi modules must have identical cpha bits. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. see figure 15-13 . reset sets the cpha bit. when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its da ta, once the transmission begins, no new data is allowed into the shift register from the data register. therefore, the slave data register must be loaded with the desired transmit data before the falling edge of ss . any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. when cpha = 1 for a slave, the first ed ge of the spsck indica tes the beginning of the transmission. the same applies when ss is high for a slave. the miso pin is held in a high-impedance state, and the incoming spsck is ignored. in certain cases, it may also cause the modf flag to be set. see 15.6.2 mode fault error . a logic 1 on the ss pin does not in any way affect the state of the spi state machine. address: $0044 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r= reserved figure 15-14. spi control register (spcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 229 spwom ? spi wired-or mode bit this read/write bit disables the pull up devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsck, mosi, and miso pins spe ? spi enable bit this read/write bit enables the spi modul e. clearing spe causes a partial reset of the spi. see 15.8 resetting the spi . reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable bit this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 15.12.2 spi status and control register the spi status and control register ( spscr) contains flags to signal these conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also co ntains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate address: $0045 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write:r rrr reset:00001000 r=reserved figure 15-15. spi status and control register (spscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 230 serial peripheral interface module (spi) motorola sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt (dmas = 0), the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests. 0 = modf and ovrf cannot generate cpu interrupt requests. ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bit by reading the spi status and control regi ster (spscr) with modf set and then writing to the spi control register (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request or an spte dma service request if the sptie bit in the spi control register is set also. note: do not write to the spi data register unless the spte bit is high. for an idle master of idle slave that has no data loaded into its transmit buffer, the spte will be set again within two bus cycles since the transmit buffer empties into the shift register. this allo ws the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola serial peripheral interface module (spi) 231 the transmission is completed. this im plies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does no t clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not available as a general-purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-purpose i/o regardless of the value of modfen. see 15.11.4 ss (slave select) . if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. see 15.6.2 mode fault error . spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 15-4 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor table 15-4. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------------------- = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral in terface module (spi) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 232 serial peripheral interface module (spi) motorola 15.12.3 spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes data into the transmit data register. reading the spi da ta register reads data from the receive data register. the transmit data and receive data registers are separate registers that can contain different values. see figure 15-3 . r7:r0/t7:t0 ? receive/transmit data bits note: do not use read-modify-write instructions on the spi data register since the register read is not the same as the register written. address: $0046 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 15-16. spi data register (spdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 233 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 16. timer interface a (tima) 16.1 introduction this section describes the timer interface module a (tima). the tima is a 4-channel timer that provides: timing reference with input capture output compare pulse-width modulator functions figure 16-2 is a block diagram of the tima. 16.2 features features of the tima include: four input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse-widt h modulator (pwm) signal generation programmable tima clock input: ? 7-frequency internal bus clock prescaler selection ? external tima clock input (4-mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow tima counter stop and reset bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 234 timer interface a (tima) motorola timer interface a (tima) figure 16-1. block diagram highlighting tima block and pins clock generator module system integration module serial communications interface module serial peripheral interface module (2) timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 112 bytes user flash ? 32,256 bytes user ram ? 768 bytes monitor rom ? 240 bytes user flash vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq v ss v dd v ddad pta7?pta0 pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b (1) pte1/tch0b (1) pte0/tclkb (1) ptf5/txd ptf4/rxd ptf3/miso (1) ptf2/mosi (1) ptf1/ss (1 ) ptf0/spsck (1) timer interface module b pulse-width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9(1) ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssad v dda v ssa (3) pwmgnd v refl (3) v refh notes: 1. these pins are not avail able in the 56-pin sdip package. 2. this module is not avail able in the 56-pin sdip package. 3. in the 56-pin sdip package, these pins are bonded together. single break module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) features mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 235 figure 16-2. tima block diagram pte3/tclka prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a pte4 tof toie inter- channel 0 tmodh:tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock pte4/tch0a pte5/tch1a pte6/tch2a pte7/tch3a logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h:tch1l ms1a els1b els1a pte5 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic 16-bit comparator 16-bit latch tch2h:tch2l ms2a els2b els2a pte6 channel 2 tov2 ch2ie ch2f ch2max ms2b logic inter- rupt logic 16-bit comparator 16-bit latch tch3h:tch3l els3b els3a pte7 channel 3 tov3 ch3ie ch3f ch3max logic inter- rupt logic ms3a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 236 timer interface a (tima) motorola addr. register name bit 7 6 5 4 3 2 1 bit 0 $000e tima status/control register (tasc) see page 245. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $000f tima counter register high (tacnth) see page 247. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0010 tima counter register low (tacntl) see page 247. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0011 tima counter modulo register high (tamodh) see page 248. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0012 tima counter modulo register low (tamodl) see page 248. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0013 tima channel 0 status/control register (tasc0) see page 249. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0014 tima channel 0 register high (tach0h) see page 252. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0015 tima channel 0 register low (tach0l) see page 252. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0016 tima channel 1 status/control register (tasc1) see page 249. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $0017 tima channel 1 register high (tach1h) see page 252. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0018 tima channel 1 register low (tach1l) see page 252. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $0019 tima channel 2 status/control register (tasc2) see page 249. read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 0 0 0 0 0 0 0 0 r = reserved figure 16-3. tim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 237 16.3 functional description figure 16-2 shows the tima structure. the central component of the tima is the 16-bit tima counter that can operate as a free-running counter or a modulo up-counter. the tima counter provides t he timing reference for the input capture and output compare functions. the tima counter modulo registers, tamodh?tamodl, control the modulo value of the tima counter. software can read the tima counter value at any time without affecting the counting sequence. the four tima channels are programmabl e independently as input capture or output compare channels. 16.3.1 tima counter prescaler the tima clock source can be one of the seven prescaler outputs or the tima clock pin, pte3/tclka. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tima status and control register select the tima clock source. $001a tima channel 2 register high (tach2h) see page 252. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $001b tima channel 2 register low (tach2l) see page 252. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset $001c tima channel 3 status/control register (tasc3) see page 249. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset: 0 0 0 0 0 0 0 0 $001d tima channel 3 register high (tach3h) see page 252. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $001e tima channel 3 register low (tach3l) see page 252. read: bit 7 6 5 4 3 2 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved figure 16-3. tim i/o register summary (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 238 timer interface a (tima) motorola 16.3.2 input capture an input capture function has three basic parts: 1. edge select logic 2. input capture latch 3. 16-bit counter two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the polarity of the active edge is programmable. the level transition which tr iggers the counter transfer is defined by the corresponding input edge bits (elsxb and elsxa in tasc0?tasc3 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channe l, the tima latches the contents of the tima counter into the tima channel registers, tachxh?tachxl. input captures can generate tima cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. the free-running counter contents are transferred to the tima channel status and control register (tachxh?tachxl, see 16.7.5 tima channel registers ) on each proper signal transition regardless of whether the tima channel flag (ch0f?ch3f in tasc0?tasc3 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register two bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a period, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establish a time reference. in this case, an input capture function is used in conjunction with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 16.7.5 tima channel registers ). because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the input capture channel registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 239 16.3.3 output compare with the output compare function, the ti ma can generate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the registers of an output compare channel, the tima can set, clear, or toggle the channel pin. output compares can generate tima cpu interrupt requests. 16.3.3.1 unbuffere d output compare any output compare channel can generate unbuffered output compare pulses as described in 16.3.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tima channel registers. an unsynchronized write to the tima channel registers to change an output compare value could cause incorrect oper ation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tima overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tima may pass the new value before it is written. use this method to synchronize unbuffer ed changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 16.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte4/tch0a pin. the tima channel registers of the linked pair alternately control the output. setting the ms0b bit in tima channel 0 st atus and control register (tasc0) links channel 0 and channel 1. the output com pare value in the tima channel 0 registers initially controls the output on the pte4/tch0a pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 240 timer interface a (tima) motorola channel registers (0 or 1) that control the output are the ones written to last. tasc0 controls and monitors the buffered output compare function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte5/tch1a, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the pte6/tch2a pin. the tima channel registers of the linked pair alternately control the output. setting the ms2b bit in tima channel 2 st atus and control register (tasc2) links channel 2 and channel 3. the output com pare value in the tima channel 2 registers initially controls the output on the pte6/tch2a pin. writing to the tima channel 3 registers enables the tima channel 3 registers to synchronously control the output after the tima overflows. at each subsequent overflow, the tima channel registers (2 or 3) that control the output are the ones written to last. tasc2 controls and monitors the buffered output compare function, and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, pte7/tch3a, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new val ue to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 16.3.4 pulse-width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tima can generate a pwm signal. the value in the tima counter modulo registers determines the period of the pwm si gnal. the channel pin toggles when the counter reaches the value in the tima counter modulo registers. the time between overflows is the period of the pwm signal. as figure 16-4 shows, the output compare value in the tima channel registers determines the pulse width of the pw m signal. the time between overflow and output compare is the pulse width. progr am the tima to clear the channel pin on output compare if the polarity of the pwm pulse is 1 (elsxa = 0). program the tima to set the pin if the polarity of the pwm pulse is 0 (elsxa = 1). the value in the tima counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tima counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 16.7.1 tima status and control register ). the value in the tima channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tima channel registers produces a duty cycle of 128/256 or 50 percent. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 241 figure 16-4. pwm period and pulse width 16.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 16.3.4 pulse-width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing t he new pulse width value over the value currently in the tima channel registers. an unsynchronized write to the tima c hannel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter re aches the old value but after the counter reaches the new value prevents any compar e during that pwm period. also, using a tima overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tima may pass the new value before it is written to the tima channel registers. use this method to synchronize unbuffer ed changes in the pwm pulse width on channel x: when changing to a shorter pulse wi dth, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. tchx period pulse width overflow overflow overflow output compare output compare output compare tchx polarity = 1 (elsxa = 0) polarity = 0 (elsxa = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 242 timer interface a (tima) motorola 16.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte4/tch0a pin. the tima channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tima channel 0 st atus and control register (tasc0) links channel 0 and channel 1. the tima channel 0 registers initially control the pulse width on the pte4/tch0a pin. writing to the tima channel 1 registers enables the tima channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (0 or 1) that control the pulse width are the ones written to last. tasc0 controls and monitors the buffered pwm function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte5/tch1a, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the pte6/tch2a pin. the tima channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in tima channel 2 st atus and control register (tasc2) links channel 2 and channel 3. the tima channel 2 registers initially control the pulse width on the pte6/tch2a pin. writing to the tima channel 3 registers enables the tima channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (2 or 3) that control the pulse width are wr itten to last. tasc2 controls and monitors the buffered pwm function, and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, pte7/tch3a, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 16.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tima status and control register (tasc): a. stop the tima counter by setting the tima stop bit, tstop. b. reset the tima counter and prescaler by setting the tima reset bit, trst. 2. in the tima counter modulo registers (tamodh?tamodl), write the value for the required pwm period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 243 3. in the tima channel x registers (tachxh?tachxl), write the value for the required pulse width. 4. in tima channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb?msxa. (see table 16-2 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (polarity 1 ? to clear output on compare) or 1:1 (polarity 0 ? to set output on compare) to the edge /level select bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 16-2 .) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tima status control register (tasc), clear the tima stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tima channel 0 registers (tach0h?tach0l) initially control the buffered pwm output. tima status control register 0 (tasc0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tima channel 2 registers (tach2h?tach2l) initially control the buffered pwm output. tima status control register 2 (tasc2) controls and monitors the pwm signal from the linked channels. ms2b takes priority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tima overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the re sult is a 0 percent duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100 percent duty cycle output. (see 16.7.4 tima channel status and control registers .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 244 timer interface a (tima) motorola 16.4 interrupts these tima sources can generate interrupt requests: tima overflow flag (tof) ? the timer overflow flag (tof) bit is set when the tima counter reaches the modul o value programmed in the tima counter modulo registers. the tima overflow interrupt enable bit, toie, enables tima overflow interrupt requests. tof and toie are in the tima status and control registers. tima channel flags (ch3f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tima cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. 16.5 wait mode the wait instruction puts the mcu in low power-consumption standby mode. the tima remains active after the execution of a wait instruction. in wait mode, the tima registers are not accessible by the cpu. any enabled cpu interrupt request from the tima can bring the mcu out of wait mode. if tima functions are not required during wait mode, reduce power consumption by stopping the tima before executing the wait instruction. 16.6 i/o signals port e shares five of its pins with the tima: pte3/tclka is an external clock input to the tima prescaler. the four tima channel i/o pins are pte4/tch0a, pte5/tch1a, pte6/tch2a, and pte7/tch3a. 16.6.1 tima clock pin (pte3/tclka) pte3/tclka is an external clock input that can be the clock source for the tima counter instead of the prescaled internal bus clock. select the pte3/tclka input by writing logic 1s to the three prescaler select bits, ps[2:0]. see 16.7.1 tima status and control register . the maximum tclk frequency is the least: 4 mhz or bus frequency 2. pte3/tclka is available as a general-purpose i/o pin when not used as the tima clock input. when the pte3/tclka pin is the tima clock input, it is an input regardless of the state of the ddre3 bit in data direction register e. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 245 16.6.2 tima channel i/o pins (pte4/tch0a?pte7/tch3a) each channel i/o pin is programmable inde pendently as an input capture pin or an output compare pin. pte2/tch0 and pte4/tch2 can be configured as buffered output compare or buffered pwm pins. 16.7 i/o registers these input/output (i/o) registers control and monitor tima operation: tima status and control register (tasc) tima control registers (tacnth?tacntl) tima counter modulo regi sters (tamodh?tamodl) tima channel status and control registers (tasc0, tasc1, tasc2, and tasc3) tima channel registers (tach0h?tach0l, tach1h?tach1l, tach2h?tach2l, and tach3h?tach3l) 16.7.1 tima status and control register the tima status and control register: enables tima overflow interrupts flags tima overflows stops the tima counter resets the tima counter prescales the tima counter clock tof ? tima overflow flag this read/write flag is set when the tima counter reaches the modulo value programmed in the tima counter modulo registers. clear tof by reading the tima status and control register when tof is set and then writing a logic 0 to tof. if another tima overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request address: $000e bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset:00100000 r= reserved figure 16-5. tima status and control register (tasc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 246 timer interface a (tima) motorola cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = tima counter has reached modulo value. 0 = tima counter has not reached modulo value. toie ? tima overflow interrupt enable bit this read/write bit enables tima overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tima overflow interrupts enabled 0 = tima overflow interrupts disabled tstop ? tima stop bit this read/write bit stops the tima counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tima counter until software clears the tstop bit. 1 = tima counter stopped 0 = tima counter active note: do not set the tstop bit before entering wait mode if the tima is required to exit wait mode. also when the tstop bit is set and the timer is configured for input capture operation, input captures are in hibited until the tstop bit is cleared. trst ? tima reset bit setting this write-only bit resets the tima counter and the tima prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tima counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tima counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tima counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pte3/tclka pin or one of the seven prescaler outputs as the input to the tima counter as table 16-1 shows. reset clears the ps[2:0] bits. table 16-1. prescaler selection ps[2:0] tima clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 pte3/tclka f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 247 16.7.2 tima counter registers the two read-only tima counter registers contain the high and low bytes of the value in the tima counter. reading the high byte (tacnth) latches the contents of the low byte (tacntl) into a buffer. subsequent reads of tacnth do not affect the latched tacntl value until tacntl is read. reset clears the tima counter registers. setting the tima reset bit (trst) also clears the tima counter registers. note: if tacnth is read during a break interrupt, be sure to unlatch tacntl by reading tacntl before exiting the break interrupt. otherwise, tacntl retains the value latched during the break. register name and address: tacnth ? $000f bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write:rrrrrrrr reset:00000000 register name and address: tacntl ? $0010 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write:rrrrrrrr reset:00000000 r= reserved figure 16-6. tima counter registers (tacnth and tacntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 248 timer interface a (tima) motorola 16.7.3 tima counter modulo registers the read/write tima modulo registers contain the modulo value for the tima counter. when the tima counter reaches the modulo value, the overflow flag (tof) becomes set, and the tima counter resumes counting from $0000 at the next timer clock. writing to the high byte (tamodh) inhibits the tof bit and overflow interrupts until the low byte (tam odl) is written. reset sets the tima counter modulo registers. note: reset the tima counter before writing to the tima counter modulo registers. 16.7.4 tima channel status and control registers each of the tima channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tima overflow selects 0 percent and 100 percent pwm duty cycle selects buffered or unbuffered output compare/pwm operation register name and address: tamodh ? $0011 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address: tamodl ? $0012 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 16-7. tima counter modulo registers (tamodh and tamodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 249 chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pi n. when channel x is an output compare channel, chxf is set when the value in the tima counter registers matches the value in the tima channel x registers. when chxie = 1, clear chxf by readi ng tima channel x status and control register with chxf set, and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x register name and address: tasc0 ? $0013 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address: tasc1 ? $0016 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 register name and address: tasc2 ? $0019 bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 register name and address: tasc3 ? $001c bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 r reset:00000000 r= reserved figure 16-8. tima channel status and control registers (tasc0?tasc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 250 timer interface a (tima) motorola chxie ? channel x interrupt enable bit this read/write bit enables tima cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tima channel 0 and tima channel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1a pin to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3a pin to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 16-2 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchxa pin once pwm, input capture, or output compare operation is enabled. see table 16-2 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by wr iting to the msxb or msxa bit, set the tstop and trst bits in the tima status and control register (tasc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e, and pin ptex/tchxa is available as a general-purpose i/o pin. however, channel x is at a state determined by these bits and becomes transparent to the respective pin when pwm, input capture, or output compare mode is enabled. table 16-2 shows how elsxb and elsxa wo rk. reset clears the elsxb and elsxa bits. note: before enabling a tima channel register for input capture operation, make sure that the ptex/tachx pin is stabl e for at least two bus clocks. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 251 tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tima counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tima counter overflow. 0 = channel x pin does not toggl e on tima counter overflow. note: when tovx is set, a tima counter overfl ow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx is 1 and clear output on compare is selected, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100 percent. as figure 16-9 shows, chxmax bit takes effect in the cycle after it is set or cleared. the output stays at 100 percent duty cycle level until the cycle after chxmax is cleared. table 16-2. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initialize timer output level high x1 00 pin under port control; initialize timer output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 00 output compare or pwm software compare only 01 01 toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 252 timer interface a (tima) motorola figure 16-9. chxmax latency 16.7.5 tima channel registers these read/write registers contain the captured tima counter value of the input capture function or the output compare value of the output compare function. the state of the tima channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tima channel x registers (tachxh) inhibits input captures until the low byte (tachxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tima channel x registers (tachxh) inhibits output compar es until the low byte (tachxl) is written. output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare tovx register name and address: tach0h ? $0014 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tach0l ? $0015 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 16-10. tima channel registers (tach0h/l?tach3h/l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface a (tima) 253 register name and address: tach1h ? $0017 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tach1l ? $0018 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address: tach2h ? $001a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tach2l ? $001b bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address: tach3h ? $001d bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tach3l ? $001e bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 16-10. tima channel registers (tach0h/l?tach3h/l) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface a (tima) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 254 timer interface a (tima) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 255 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 17. timer interface b (timb) 17.1 introduction this section describes the timer interface module b (timb). the timb is a 2-channel timer that provides: timing reference with input capture output compare pulse-width modulation functions figure 17-2 is a block diagram of the timb. note: the timb module is not available in the 56-pin shrink dual in-line package (sdip). 17.2 features features of the timb include: two input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse-width modulation (pwm) signal generation programmable timb clock input: ? 7-frequency internal bus clock prescaler selection ? external timb clock input (4-mhz maximum frequency) free-running or modulo up-count operation toggle any channel pin on overflow timb counter stop and reset bits 17.3 functional description figure 17-2 shows the timb structure. the central component of the timb is the 16-bit timb counter that can operate as a free-running counter or a modulo up-counter. the timb counter provides t he timing reference for the input capture and output compare functions. the timb counter modulo registers, tbmodh?tbmodl, control the modulo value of the timb counter. software can read the timb counter value at any time without affecting the counting sequence. the two timb channels are programmable independently as input capture or output compare channels. note: the timb module is not avai lable in the 56-pin sdip. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 256 timer interface b (timb) motorola timer interface b (timb) figure 17-1. block diagram highlighting timb block and pins clock generator module system integration module serial communications interface module serial peripheral interface module (2) timer interface module a low-voltage inhibit module power-on reset module computer operating properly module arithmetic/logic unit cpu registers m68hc08 cpu control and status registers ? 112 bytes user flash ? 32,256 bytes user ram ? 768 bytes monitor rom ? 240 bytes user flash vector space ? 46 bytes irq module power pta ddra ddrb ptb ddrc ptc ptd ddre pte ptf ddrf internal bus osc1 osc2 cgmxfc rst irq v ss v dd v ddad pta7?pta0 pte7/tch3a pte6/tch2a pte5/tch1a pte4/tch0a pte3/tclka pte2/tch1b (1) pte1/tch0b (1) pte0/tclkb (1) ptf5/txd ptf4/rxd ptf3/miso (1) ptf2/mosi (1) ptf1/ss (1) ptf0/spsck (1 ) timer interface module b pulse-width modulator module ptb7/atd7 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1/atd9(1) ptc0/atd8 ptd6/is3 ptd5/is2 ptd4/is1 ptd3/fault4 ptd2/fault3 ptd1/fault2 ptd0/fault1 pwm6?pwm1 analog-to-digital converter module v ssad v dda v ssa (3) pwmgnd v refl (3) v refh notes: 1. these pins are not available in the 56-pin sdip package. 2. this module is not avail able in the 56-pin sdip package. 3. in the 56-pin sdip package, these pins are bonded together. single break module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 257 figure 17-2. timb block diagram prescaler prescaler select tclk internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a pte1 tof toie inter- channel 0 tmodh:tmodl trst tstop tov0 ch0ie ch0f ch0max ms0b 16-bit counter bus clock pte0/tclkb pte1/tch0b pte2/tch1b logic rupt logic inter- rupt logic 16-bit comparator 16-bit latch tch1h:tch1l ms1a els1b els1a pte2 channel 1 tov1 ch1ie ch1f ch1max logic inter- rupt logic addr. register name bit 7 6 5 4 3 2 1 bit 0 $0051 timb status/control register (tbsc) see page 265. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset: 0 0 1 0 0 0 0 0 $0052 timb counter register high (tbcnth) see page 267. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0053 timb counter register low (tbcntl) see page 267. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: r r r r r r r r reset: 0 0 0 0 0 0 0 0 $0054 timb counter modulo register high (tbmodh) see page 268. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 r= reserved figure 17-3. timb i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 258 timer interface b (timb) motorola 17.3.1 timb counter prescaler the timb clock source can be one of the seven prescaler outputs or the timb clock pin, pte0/tclkb . the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the timb status and control register select the timb clock source. 17.3.2 input capture an input capture function has three basic parts: 1. edge select logic 2. input capture latch 3. 16-bit counter two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. the polarity of the active edge is $0055 timb counter modulo register low (tbmodl) see page 268. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0056 timb channel 0 status/control register (tbsc0) see page 269. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 0 0 0 0 0 0 0 0 $0057 timb channel 0 register high (tbch0h) see page 272. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0058 timb channel 0 register low (tbch0l) see page 272. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0059 timb channel 1 status/control register (tbsc1) see page 269. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset: 0 0 0 0 0 0 0 0 $005a timb channel 1 register high (tbch1h) see page 272. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $005b timb channel 1 register low (tbch1l) see page 272. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset addr. register name bit 7 6 5 4 3 2 1 bit 0 r= reserved figure 17-3. timb i/o register summary (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 259 programmable. the level transition which tr iggers the counter transfer is defined by the corresponding input edge bits (elsxb and elsxa in tbsc0?tbsc1 control registers with x referring to the active channel number). when an active edge occurs on the pin of an input capture channe l, the timb latches the contents of the timb counter into the timb channel registers, tchxh?tchxl. input captures can generate timb cpu interrupt requests. software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. the free-running counter contents are transferred to the timb channel status and control register (tbchxh?tbchxl, see 17.7.5 timb channel registers ) on each proper signal transition regardless of whether the timb channel flag (ch0f?ch1f in tbsc0?tbsc1 registers) is set or clear. when the status flag is set, a cpu interrupt is generated if enabled. the value of the count latched or ?captured? is the time of the event. because this value is stored in the input capture register two bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a period, two successive edges of the same polarity are captured. to measure a pulse width, two alternate polarity edges are captured. software should track the overflows at the 16-bit module counter to extend its range. another use for the input capture function is to establish a time reference. in this case, an input capture function is used in conjunction with an output compare function. for example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. a number corresponding to the desired delay is added to this captured value and stored to an output compare register (see 17.7.5 timb channel registers ). because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. reset does not affect the contents of the input capture channel register (tbchxh?tbchxl). 17.3.3 output compare with the output compare function, the ti mb can generate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the registers of an output compare channel, the timb can set, clear, or toggle the channel pin. output compares can generate timb cpu interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 260 timer interface b (timb) motorola 17.3.3.1 unbuffere d output compare any output compare channel can generate unbuffered output compare pulses as described in 17.3.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the timb channel registers. an unsynchronized write to the timb channel registers to change an output compare value could cause incorrect oper ation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a timb overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the timb may pass the new value before it is written. use this method to synchronize unbuffer ed changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 17.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte1/tch0b pin. the timb channel registers of the linked pair alternately control the output. setting the ms0b bit in timb channel 0 st atus and control register (tbsc0) links channel 0 and channel 1. the output com pare value in the timb channel 0 registers initially controls the output on the pte1/tch0b pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchronously control the output after the timb overflows. at each subsequent overflow, the timb channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1b, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 261 active channel to prevent writing a new val ue to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 17.3.4 pulse-width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the timb can generate a pwm signal. the value in the timb counter modulo registers determines the period of the pwm si gnal. the channel pin toggles when the counter reaches the value in the timb counter modulo registers. the time between overflows is the period of the pwm signal. as figure 17-4 shows, the output compare value in the timb channel registers determines the pulse width of the pw m signal. the time between overflow and output compare is the pulse width. progr am the timb to clear the channel pin on output compare if the polarity of the pwm pulse is 1 (elsxa = 0). program the timb to set the pin if the polarity of the pwm pulse is 0 (elsxa = 1). figure 17-4. pwm period and pulse width the value in the timb counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the timb counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000 (see 17.7.1 timb status and control register ). the value in the timb channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the timb channel registers produces a duty cycle of 128/256 or 50 percent. tchx period pulse width overflow overflow overflow output compare output compare output compare tchx polarity = 1 (elsxa = 0) polarity = 0 (elsxa = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 262 timer interface b (timb) motorola 17.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 17.3.4 pulse-width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing t he new pulse width value over the value currently in the timb channel registers. an unsynchronized write to the timb c hannel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter re aches the old value but after the counter reaches the new value prevents any compar e during that pwm period. also, using a timb overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the timb may pass the new value before it is written to the timb channel registers. use this method to synchronize unbuffer ed changes in the pwm pulse width on channel x: when changing to a shorter pulse wi dth, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 17.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte1/tch0b pin. the timb channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in timb channel 0 st atus and control register (tbsc0) links channel 0 and channel 1. the timb channel 0 registers initially control the pulse width on the pte1/tch0b pin. writing to the timb channel 1 registers enables the timb channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timb channel registers (0 or 1) that control the pulse width are the ones written to last. tbsc0 controls and monitors the buffered pwm function, and timb channel 1 status and control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) functional description mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 263 register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1b, is available as a general-purpose i/o pin. note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 17.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the timb status and control register (tbsc): a. stop the timb counter by setting the timb stop bit, tstop. b. reset the timb counter and prescaler by setting the timb reset bit, trst. 2. in the timb counter modulo registers (tbmodh?tbmodl), write the value for the required pwm period. 3. in the timb channel x registers (tbchxh?tbchxl), write the value for the required pulse width. 4. in timb channel x status and control register (tbscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb?msxa. (see table 17-2 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (polarity 1 ? to clear output on compare) or 1:1 (polarity 0 ? to set output on compare) to the edge /level select bits, elsxb?elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 17-2 .) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0 percent duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timb status control register (tbsc), clear the timb stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the timb channel 0 registers (tbch0h?tbch0l) initially control the buffered pwm output. timb status control register 0 (tbsc0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 264 timer interface b (timb) motorola clearing the toggle-on-overflow bit, tovx, inhibits output toggles on timb overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the re sult is a 0 percent duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100 percent duty cycle output. (see 17.7.4 timb channel status and control registers .) 17.4 interrupts these timb sources can generate interrupt requests: timb overflow flag (tof) ? the timer overflow flag (tof) bit is set when the timb counter reaches the modul o value programmed in the timb counter modulo registers. the timb overflow interrupt enable bit, toie, enables timb overflow interrupt requests. tof and toie are in the timb status and control registers. timb channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x timb cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. 17.5 wait mode the wait instruction puts the mcu in low-power standby mode. the timb remains active after the execution of a wait instruction. in wait mode, the timb registers are not accessible by the cpu. any enabled cpu interrupt request from the timb can bring the mcu out of wait mode. if timb functions are not required during wait mode, reduce power consumption by stopping the timb before executing the wait instruction. 17.6 i/o signals port e shares three of its pins with the timb: pte0/tclkb is an external clock input to the timb prescaler. the two timb channel i/o pins are pte1/tch0b and pte2/tch1b. 17.6.1 timb clock pin (pte0/tclkb) pte0/tclkb is an external clock input that can be the clock source for the timb counter instead of the prescaled internal bus clock. select the pte0/tclkb input by writing 1s to the three prescaler select bits, ps[2:0]. see 17.7.1 timb status and control register . the maximum tclk frequency is the least: 4 mhz or bus frequency 2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 265 pte0/tclkb is available as a general-pur pose i/o pin or adc channel when not used as the timb clock input. when the pte0/tclkb pin is the timb clock input, it is an input regardless of the state of the ddre0 bit in data direction register e. 17.6.2 timb channel i/o pins (pte1/tch0b?pte2/tch1b) each channel i/o pin is programmable inde pendently as an input capture pin or an output compare pin. pte1/tch0b and pte2/tch1b can be configured as buffered output compare or buffered pwm pins. 17.7 i/o registers these input/output (i/o) registers control and monitor timb operation: timb status and control register (tbsc) timb control registers (tbcnth?tbcntl) timb counter modulo regi sters (tbmodh?tbmodl) timb channel status and control registers (tbsc0 and tbsc1) timb channel registers (tbch0h?tbch0l and tbch1h?tbch1l) 17.7.1 timb status and control register the timb status and control register: enables timb overflow interrupts flags timb overflows stops the timb counter resets the timb counter prescales the timb counter clock tof ? timb overflow flag this read/write flag is set when the timb counter reaches the modulo value programmed in the timb counter modulo registers. clear tof by reading the timb status and control register when tof is set and then writing a logic 0 to tof. if another timb overflow occurs before the clearing sequence is complete, address: $0051 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst r reset:00100000 r= reserved figure 17-5. timb status and control register (tbsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 266 timer interface b (timb) motorola then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = timb counter has reached modulo value. 0 = timb counter has not reached modulo value. toie ? timb overflow interrupt enable bit this read/write bit enables timb overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = timb overflow interrupts enabled 0 = timb overflow interrupts disabled tstop ? timb stop bit this read/write bit stops the timb counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the timb counter until software clears the tstop bit. 1 = timb counter stopped 0 = timb counter active note: do not set the tstop bit before entering wait mode if the timb is required to exit wait mode. also, when the tstop bit is set and the timer is configured for input capture operation, input captures ar e inhibited until tstop is cleared. trst ? timb reset bit setting this write-only bit resets the timb counter and the timb prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the timb counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and timb counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the timb counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pte0/tclkb pin or one of the seven prescaler outputs as the input to the timb counter as table 17-1 shows. reset clears the ps[2:0] bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 267 17.7.2 timb counter registers the two read-only timb counter registers contain the high and low bytes of the value in the timb counter. reading the high byte (tbcnth) latches the contents of the low byte (tbcntl) into a buffer. subsequent reads of tbcnth do not affect the latched tbcntl value until tbcntl is read. reset clears the timb counter registers. setting the timb reset bit (trst) also clears the timb counter registers. note: if tbcnth is read during a break interrupt, be sure to unlatch tbcntl by reading tbcntl before exiting the break interrupt. otherwise, tbcntl retains the value latched during the break. table 17-1. prescaler selection ps[2:0] timb clock source 000 internal bus clock 1 001 internal bus clock 2 010 internal bus clock 4 011 internal bus clock 8 100 internal bus clock 16 101 internal bus clock 32 110 internal bus clock 64 111 pte0/tclkb register name and address: tbcnth ? $0052 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write:rrrrrrrr reset:00000000 register name and address: tbcntl ? $0053 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write:rrrrrrrr reset:00000000 r = reserved figure 17-6. timb counter registers (tbcnth and tbcntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) data sheet mc68hc908mr32 ? mc68HC908MR16 ? rev. 6.0 268 timer interface b (timb) motorola 17.7.3 timb counter modulo registers the read/write timb modulo registers contain the modulo value for the timb counter. when the timb counter reaches the modulo value, the overflow flag (tof) becomes set, and the timb counter resumes counting from $0000 at the next timer clock. writing to the high byte (tbmodh) inhibits the tof bit and overflow interrupts until the low byte (tbm odl) is written. reset sets the timb counter modulo registers. note: reset the timb counter before writing to the timb counter modulo registers. 17.7.4 timb channel status and control registers each of the timb channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on timb overflow selects 0 percent and 100 percent pwm duty cycle selects buffered or unbuffered output compare/pwm operation register name and address: tbmodh ? $0054 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 register name and address: tbmodl ? $0055 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 17-7. timb counter modulo registers (tbmodh and tbmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 269 chxf ? channel x flag when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pi n. when channel x is an output compare channel, chxf is set when the value in the timb counter registers matches the value in the timb channel x registers. when chxie = 1, clear chxf by readi ng timb channel x status and control register with chxf set, and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables timb cpu interrupts on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the timb channel 0. setting ms0b disables the channel 1 status and control register and reverts tch1b to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled register name and address: tbsc0 ? $0056 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 register name and address: tbsc1 ? $0059 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 r reset:00000000 r= reserved figure 17-8. timb channel status and control registers (tbsc0?tbsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 270 timer interface b (timb) motorola msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 17-2 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin once pwm, input capture, or output compare operation is enabled. see table 17-2 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by wr iting to the msxb or msxa bit, set the tstop and trst bits in the timb status and control register (tbsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e, and pin ptex/tchxb is available as a general-purpose i/o pin. however, channel x is at a state determined by these bits and becomes transparent to the respective pin when pwm, input capture, or output compare mode is enabled. table 17-2 shows how elsxb and elsxa wo rk. reset clears the elsxb and elsxa bits. note: before enabling a timb channel register for input capture operation, make sure that the ptex/tbchx pin is stabl e for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the timb counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on timb counter overflow. 0 = channel x pin does not toggl e on timb counter overflow. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) i/o registers mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola timer interface b (timb) 271 note: when tovx is set, a timb counter overfl ow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx is 1 and clear output on compare is selected, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100 percent. as figure 17-9 shows, chxmax bit takes effect in the cycle after it is set or cleared. the output stays at 100 percent duty cycle level until the cycle after chxmax is cleared. figure 17-9. chxmax latency table 17-2. mode, edge, and level selection msxb:msxa elsxb:elsx a mode configuration x0 00 output preset pin under port control; initialize timer output level high x1 00 pin under port control; initialize timer output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 00 output compare or pwm softare compare only 01 01 toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare tovx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface b (timb) data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 272 timer interface b (timb) motorola 17.7.5 timb channel registers these read/write registers contain the captured timb counter value of the input capture function or the output compare value of the output compare function. the state of the timb channel registers after reset is unknown. in input capture mode (msxb?msxa = 0:0), reading the high byte of the timb channel x registers (tbchxh) inhibits input captures until the low byte (tbchxl) is read. in output compare mode (msxb?msxa 0:0), writing to the high byte of the timb channel x registers (tbchxh) inhibits output compar es until the low byte (tbchxl) is written. register name and address: tbch0h ? $0057 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tbch0l ? $0058 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset register name and address: tbch1h ? $005a bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset register name and address: tbch1l ? $005b bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 17-10. timb channel registers (tbch0h/l?tbch1h/l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola development support 273 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 18. development support 18.1 introduction this section describes the break module, the monitor read-only memory (mon), and the monitor mode entry methods. 18.2 break module (brk) the break module (brk) can generate a brea k interrupt that stops normal program flow at a defined address to enter a background program. features include: accessible input/output (i/o) registers during the break interrupt central processor unit (cpu) generated break interrupts software-generated break interrupts computer operating properly (cop ) disabling during break interrupts 18.2.1 functional description when the internal address bus matches the value written in the break address registers, the break module issues a br eakpoint signal to the cpu. the cpu then loads the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). these events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller unit (mcu) to normal operation. figure 18-1 shows the structure of the break module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 274 development support motorola figure 18-1. break module block diagram iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 277. read: rrrrrrbwr write: reset: 0 $fe03 sim break flag control register (sbfcr) see page 278. read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) see page 276. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) see page 276. read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) see page 276. read: brke brka 000000 write: reset:00000000 not e : writ i ng a 0 c l ears bw. = unimplemented r = reserved figure 18-2. i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support break module (brk) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola development support 275 18.2.1.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. 18.2.1.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 18.2.1.3 tim1 and tim2 during break interrupts a break interrupt stops the timer counters. 18.2.1.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 18.2.2 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 18.2.2.1 wait mode if enabled, the break module is active in wa it mode. in the break routine, the user can subtract one from the return address on the stack if sbsw is set. clear the bw bit by writing logic 0 to it. 18.2.2.2 stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. 18.2.3 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) sim break status register (sbsr) sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 276 development support motorola 18.2.3.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = when read, break address match 0 = when read, no break address match 18.2.3.2 break address registers the break address registers (brkh and brkl) contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 18-3. break status and control register (brkscr) address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 18-4. break address register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 18-5. break address register low (brkl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support break module (brk) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola development support 277 18.2.3.3 break status register the break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. bw ? break wait bit this read/write bit is set when a break interrupt causes an exit from wait mode. clear bw by writing a logic 0 to it. reset clears bw. 1 = break interrupt during wait mode 0 = no break interrupt during wait mode bw can be read within the break interrupt routine. the user can modify the return address on the stack by subtractin g 1 from it. the following code is an example. this code works if the h register was stacked in the break interrupt routine. execute this code at the end of the break interrupt routine. address: $fe00 bit 7654321bit 0 read: rrrrrrbwr write: reset: 0 figure 18-6. sim break status register (sbsr) hibyte equ 5 lobyte equ 6 ; if not bw, do rti brclr bw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not 0, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte also. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 278 development support motorola 18.2.3.4 break flag control register the break flag control register (sbfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break 18.3 monitor rom (mon) the monitor rom (mon) allows complete testing of the microcontroller unit (mcu) through a single-wire interface with a ho st computer. monitor mode entry can be achieved without the use of v tst as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. features include: normal user-mode pin functionality one pin dedicated to serial commun ication between monitor rom and host computer standard mark/space non-return-to-ze ro (nrz) communication with host computer 4800 baud?28.8 kbaud communication with host computer execution of code in random-access memory (ram) or rom flash programming 18.3.1 functional description the monitor rom receives and executes commands from a host computer. figure 18-8 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 18-7. sim break flag control register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor rom (mon) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola development support 279 figure 18-8. monitor mode circuit + + + + 10 m ? x1 v dd v hi mc145407 mc74hc125 mc68HC908MR16/ rst irq cgmxfc osc1 osc2 v ssa v ss v dd pta0 v dd 10 k ? 0.1 f 0.02 f 10 k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 4.9152 mhz 10 k ? ptc2 v dd 10 k ? b a s2 position a ? bus clock = cgmxclk 4 or cgmvclk 4 s2 position b ? bus clock = cgmxclk 2 5 6 pwmgnd v ssad v refl v dda 0.1 f v dda v ddad 0.1 f v ddad v refh 0.1 f v refh ptc3 ptc4 v dd 10 k ? mc68hc908mr32 pta7 v dd 10 k ? a b s3 s1 s2 s3 position a ? parallel communication s3 position b ? serial communication f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 280 development support motorola simple monitor commands can access any memory address. in monitor mode, the mcu can execute host-computer code in ram while all mcu pins retain normal operating mode functions. all communicat ion between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. 18.3.1.1 entering monitor mode there are two methods for entering monitor: the first is the traditional m68hc08 method where v dd + v hi is applied to irq1 and the mode pins are configured appropriately. a second method, intended for in-circuit programming applications, will force entry into monitor mode without requiring high voltage on the irq1 pin when the reset vector locations of the flash are erased ($ff). note: for both methods, holding the ptc2 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50 percent duty cycle at maximum bus frequency. table 18-1 is a summary of the differences between user mode and monitor mode. 18.3.1.2 normal monitor mode table 18-2 shows the pin conditions for entering monitor mode. table 18-1. mode differences modes functions cop rest vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v dd + v hi ) is removed from the irq1 pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. $fefe $feff $fefc $fefd $fefc $fefd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 data sheet ? rev. 6.0 motorola development support 281 development support monitor rom (mon) table 18-2. monitor mode signal requirements and options irq reset (s1) $fffe /$ffff pll ptc3 ptc4 ptc2 (s2) external clock (1) cgmout bus frequency cop for serial communication (2) comment pta0 pta7 (s3) baud rate (3) (4) x gnd x x x x x x 0 0 disabled x x 0 no operation until reset goes high v tst v dd or v tst x off 1 0 0 4.9152 mhz 4.9152 mhz 2.4576 mhz disabled 1 0 9600 ptc3 and ptc2 voltages only required if irq = v tst ; ptc2 determines frequency divider x1 dna v tst v dd or v tst x off 1 0 1 9.8304 mhz 4.9152 mhz 2.4576 mhz disabled 1 0 9600 ptc3 and ptc2 voltages only required if irq = v tst ; ptc2 determines frequency divider x1 dna v dd v dd $ffff blank off x x x 9.8304 mhz 4.9152 mhz 2.4576 mhz disabled 1 0 9600 external frequency always divided by 4 x1 dna v dd or gnd v tst $ffff blank offxxx x ? ? enabledxx ? enters user mode ? will encounter an illegal address reset v dd or gnd v dd or v tst non-$ff programmed off x x x x ? ? enabled x x ? enters user mode 1. external clock is derived by a 32.768 khz cr ystal or a 4.9152/9.8304 mh z off-chip oscillator. 2. dna = does not apply, x = don?t care 3. pat0 = 1 if serial communication; pta0 = x if parallel communication 4. pta7 = 0 serial, pta7 = 1 parallel communication for security code entry f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 282 development support motorola enter monitor mode by either: executing a software interrupt instruction (swi) or applying a logic 0 and then a logic 1 to the rst pin once out of reset, the mcu waits for the ho st to send eight security bytes. after receiving the security bytes, the mcu se nds a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready to receive a command. the break signal also provides a timing refer ence to allow the host to determine the necessary baud rate. monitor mode uses alternate vectors for reset and swi. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the computer operating properly (cop) module is disabled in m onitor mode as long as v hi is applied to either the irq pin or the rst pin. (see section 14. system integration module (sim) for more information on modes of operation.) 18.3.1.3 forced monitor mode if the voltage applied to the irq1 is less than v dd + v hi the mcu will come out of reset in user mode. the menrst module is monitoring the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($ff). when the mcu comes out of reset, it is forced into monitor mode without requiring high voltage on the irq1 pin. the cop module is disabled in forced monitor mode. any reset other than a por reset will automatically force the mcu to come back to the forced monitor mode. 18.3.1.4 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 18-9 and figure 18-10 .) figure 18-9. monitor data format figure 18-10. sample monitor waveforms the data transmit and receive rate can be anywhere from 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3bit 4bit 5bit 6bit 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor rom (mon) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola development support 283 18.3.1.5 echoing as shown in figure 18-11 , the monitor rom immediately echoes each received byte back to the pta0 pin for error checking. figure 18-11. read transaction any result of a command appears after the echo of the last byte of the command. 18.3.1.6 break signal a start bit followed by nine low bits is a break signal. see figure 18-12 . when the monitor receives a break signal, it drives t he pta0 pin high for the duration of two bits before echoi ng the break signal. figure 18-12. break transaction 18.3.1.7 commands the monitor rom uses these commands (see table 18-3 ? table 18-8 ): read, read memory write, write memory iread, indexed read iwrite, indexed write readsp, read stack pointer run, run user program addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2--stop-bit delay before zero echo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 284 development support motorola table 18-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 18-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 18-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo from host data return data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor rom (mon) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola development support 285 a sequence of iread or iwrite comman ds can access a block of memory sequentially over the full 64-kbyte memory map. table 18-6. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 18-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 18-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo data data from host readsp readsp echo from host sp return sp high low run run echo from host f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 286 development support motorola 18.3.1.8 baud rate with a 4.9152-mhz crystal and the ptc2 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. if the ptc2 pin is at logic 0 during reset, the monitor baud rate is 9600. see table 18-9 . 18.3.2 security a security feature discourages unauthori zed reading of flash locations while in monitor mode. the host can bypass the se curity feature at monitor mode entry by sending eight security bytes that matc h the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note: do not leave locations $fff6?$fffd blank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pta0 . if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from fl ash. security remains bypassed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 18-13 .) upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character until after the host sends the eight security bytes. to determine whether the security code entered is correct, check to see if bit 6 of ram address $60 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device c an be reset (via power-pin reset only) and brought up in monitor mode to attempt another entry. after failing the security sequence, the flash mode can also be bulk erased by executing an erase routine that was downloaded into internal ram. the bulk erase operation clears the security code locations so that all eight security bytes become $ff. table 18-9. monitor baud rate selection vco frequency multiplier (n) 123456 monitor baud rate 4800 9600 14,400 19,200 24,000 28,800 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support monitor rom (mon) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola development support 287 figure 18-13. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 pa7 rst v dd 4096 + 32 cgmxclk cycles 24 bus cycles 256 bus cycles (minimum) 1 3 1 1 2 1 break notes: 2 = data return delay, 2 bit times 3 = wait 1 bit time before sending next byte. 3 from host from mcu 1 = echo delay, 2 bit times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . development support data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 288 development support motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola electrical specifications 289 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 19. electrical specifications 19.1 introduction this section contains electric al and timing specifications. 19.2 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. for guaranteed operating conditions, refer to 19.5 dc electrical characteristics . note: this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any volta ge higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v input high voltage v hi v dd + 4 maximum v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 290 electrical specifications motorola 19.3 functional o perating range 19.4 thermal characteristics characteristic symbol value unit operating temperature range (1) mc68hc908mr24cfu mc68hc908mr24vfu 1. see motorola representative for temperature availability. c = extended temperature range (?40 c to +85 c) v = automotive temperature range (?40 c to +105 c) t a ?40 to 85 ?40 to 105 c operating voltage range v dd 5.0 10% v characteristic symbol value unit thermal resistance, 64-pin qfp ja 76 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + p d 2 x ja w/ c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 125 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications dc electrical characteristics mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola electrical specifications 291 19.5 dc electrica l characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) all i/o pins v oh v dd ?0.8 ??v output low voltage (i load = 1.6 ma) all i/o pins v ol ??0.4v pwm pin output source current (v oh = v dd ?0.8 v) i oh ?7 ? ? ma pwm pin output sink current (v ol = 0.8 v) i ol 20 ? ? ma input high voltage, all ports, irq s, reset , osc1 v ih 0.7 x v dd ? v dd v input low voltage, all ports, irq s, reset , osc1 v il v ss ? 0.3 x v dd v v dd supply current run (3) wait (4) stop (5) i dd ? ? ? ? ? ? 30 12 700 ma ma a i/o ports high-impedance leakage current i il ?? 10 a input current (input only pins) i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf low-voltage inhibit reset (6) v lv r 1 4.0 4.35 4.65 v low-voltage reset/recover hysteresis v lv h 1 40 90 150 mv low-voltage inhibit reset recovery (v rec1 = v lv r 1 + v lv h 1 ) v rec1 4.04 4.5 4.75 v low-voltage inhibit reset v lv r 2 3.85 4.15 4.45 v low-voltage reset/recover hysteresis v lv h 2 150 210 250 mv low-voltage inhibit reset recovery (v rec2 = v lv r 2 + v lv h 2 ) v rec2 4.0 4.4 4.6 v por re-arm voltage (7) v por 0?100mv por rise time ramp rate (8) r por 0.035 ? ? v/ms por reset voltage (9) v porrst 0 700 800 v monitor mode entry voltage (on irq ) v hi v dd + 2.5 ?8.0v 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 8.2 mhz). all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly affects run i dd ; measured with all modules enabled 4. wait i dd measured using external square wave clock source (f osc = 8.2 mhz); all inputs 0.2 v fr om rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly affects wait i dd ; measured with pll and lvi enabled. 5. stop i dd measured with pll and lvi disengaged, ocs1 grounded, no port pins sourcing current. it is measured through combination of v dd , v ddad , and v dda . 6. the low-voltage inhibit reset is software selectable. refer to section 9. low-voltage inhibit (lvi) . 7. maximum is highest vo ltage that por is guaranteed. 8. if minimum v dd is not reached before the internal por is released, rst must be driven low externally until minimum v dd is reached. 9. maximum is highest vo ltage that por is possible. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 292 electrical specifications motorola 19.6 flash memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash read bus clock frequency f read (1) 0?8 mhz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm/erase to hven setup time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program hold time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (2) 1?? s flash cumulative program hv period t hv (3) ?? 4ms flash endurance (4) ? 10 k 100 k ? cycles flash data retention time (5) ? 15 100 ? years 1. f read is defined as the frequency range for which the flash memory can be read. 2. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to 0. 3. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 32) t hv maximum. 4. typical endurance was evaluated for this product family. for additional information on how motorola defines typical endurance , please refer to engineering bulletin eb619. 5. typical data retention values are based on intrinsic capabili ty of the technology measured at high temperature and de-rated to 25c using the arrhenius equation. for additional information on how motorola defines typical data retention , please refer to engineering bulletin eb618. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications control timing mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola electrical specifications 293 19.7 control timing characteristic (1) symbol min max unit frequency of operation (2) crystal option external clock option (3) f osc 1 dc (4) 8 32.8 mhz internal operating frequency f op ?8.2mhz reset input pulse width low (5) t irl 50 ? ns 1. v dd = 5.0 vdc 10%, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted 2. see 19.8 serial peripheral interface characteristics for more information. 3. no more than 10% duty cycle deviation from 50%. 4. some modules may require a minimum frequency greater than dc for proper operation; s ee appropriate table for this information. 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 294 electrical specifications motorola 19.8 serial peripheral interface characteristics diagram number (1) characteristic (2) symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc 2 enable lead time t lead(s) 15 ? ns 3 enable lag time t lag(s) 15 ? ns 4 clock (spck) high time master slave t sckh(m) t sckh(s) 100 50 ? ? ns 5 clock (spck) low time master slave t sckl(m) t sckl(s) 100 50 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ? ? ns 8 access time, slave (3) cpha = 0 chpa = 1 t a(cp0) t a(cp1) 0 0 40 20 ns 9 disable time, slave (4) t dis(s) ?25ns 10 data valid time after enable edge master slave (5) t v(m) t v(s) ? ? 10 40 ns 1. v dd = 5.0 vdc 10%, all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted; assumes 100 pf load on all spi pins 2. numbers refer to dimensions in figure 19-1 and figure 19-2 . 3. time to data active from high-impedance state 4. hold time to high-impedance state 5. with 100 pf on all spi pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications serial peripheral interface characteristics mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola electrical specifications 295 figure 19-1. spi master timing note ss pin of master held high msb in ss input spck, cpol = 0 output spck, cpol = 1 output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the sck pin. ss pin of master held high msb in ss input spck, cpol = 0 output spck, cpol = 1 output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) note: this first clock edge is generated internally, but is not seen at the sck pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 296 electrical specifications motorola figure 19-2. spi slave timing note: not defined, but normally msb of character just received slave ss input spck, cpol = 0 input spck, cpol = 1 input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined, but normally lsb of character previ ously transmitted slave ss input spck, cpol = 0 input spck, cpol = 1 input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications timer interface module characteristics mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola electrical specifications 297 19.9 timer interface m odule characteristics 19.10 clock generation module component specifications 19.11 cgm operating conditions characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ?ns characteristic symbol min typ max notes crystal load capacitance c l ??? consult crystal manufacturing data crystal fixed capacitance c 1 ? 2 * c l ? consult crystal manufacturing data crystal tuning capacitance c 2 ? 2 * c l ? consult crystal manufacturing data feedback bias resistor r b ? 22 m ? ? series resistor r s 0330 k ? 1 m ? not required filter capacitor c f ? c fact * (v dda /f xclk ) ? bypass capacitor c byp ?0.1 f? c byp must provide low ac impedance from f = f xclk /100 to 100*f vclk , so series resistance must be considered characteristic symbol min typ max unit crystal reference frequency f xclk 1?8mhz range nominal multiplier f nom ?4.9152? mhz vco center-of-range frequency f vrs 4.9152 ? 32.8 mhz vco frequency multiplier n 1 ? 15 ? vco center of range multiplier l 1 ? 15 ? vco operating frequency f vclk f vrsmin ? f vrsmax ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 298 electrical specifications motorola 19.12 cgm acquisition/lock time specifications description symbol min typ max notes filter capacitor multiply factor c fact ? 0.0154 ? f/sv acquisition mode time factor k acq ? 0.1135 ? v tracking mode time factor k trk ? 0.0174 ? v manual mode time to stable t acq ? (8*v dda )/ (f xclk *k acq) ? if c f chosen correctly manual stable to lock time t al ? (4*v dda )/ (f xclk *k trk ) ? if c f chosen correctly manual acquisition time t lock ? t acq +t al ? tracking mode entry frequency tolerance ? trk 0? 3.6% acquisition mode entry frequency tolerance ? acq 6.3% ? 7.2% lock entry frequency tolerance ? lock 0? 0.9% lock exit frequency tolerance ? unl 0.9% ? 1.8% reference cycles per acquisition mode measurement n acq ?32? reference cycles per tracking mode measurement n trk ?128? automatic mode time to stable t acq n acq /f xclk (8*v dda )/ (f xclk *k acq) ? if c f chosen correctly automatic stable to lock time t al n trk /f xclk (4*v dda )/ (f xclk *k trk ) ? if c f chosen correctly automatic lock time t lock ? t acq +t al ? pll jitter (deviation of average bus frequency over 2 ms) f j 0? (f xclk ) *(0.025%) *(n/4) n = vco freq. mult. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications analog-to-digital converter (adc) characteristics mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola electrical specifications 299 19.13 analog-to-digital conv erter (adc) c haracteristics characteristic symbol min typ max unit notes supply voltage v ddad 4.5 ? 5.5 v v ddad should be tied to the same potential as v dd via separate traces input voltages v adin 0? v ddad v v adin <= v ddad resolution b ad 10 ? 10 bits absolute accuracy a ad ?? 4 lsb includes quantization adc internal clock f adic 500 k ? 1.048 m hz t aic = 1/f adic conversion range r ad v ssad ? v ddad v power-up time t adpu 16 ? ? t aic cycles conversion time t adc 16 ? 17 t aic cycles sample time t ads 5? ? t aic cycles monotonicity m ad guaranteed zero inpu t reading z adi 000 ? 003 hex v adin = v ssad full-scale reading f adi 3fc ? 3ff hex v adin = v ddad input capacitance c adi ? ? 30 pf not tested v refh /v refl current i vref ?1.6 ? ma absolute accuracy (8-bit truncation mode) a ad ?? 1 lsb includes quantization quantization error (8-bit truncation mode) ??? + 7/8 ? 1/8 lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical s pecifications data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 300 electrical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola ordering information and mechanical specifications 301 data sheet ? mc68hc 908mr32 mc68HC908MR16 section 20. ordering informatio n and mechanical specifications 20.1 introduction this section provides ordering information for the mc68HC908MR16 and mc68hc908mr32 along with the dimensions for: 64-lead plastic quad flat pack (qfp) 56-pin shrink dual in-line package (sdip) the following figures show the latest pac kage drawings at the time of this publication. to make sure that you have the latest package specifications, contact your local motorola sales office. 20.2 order numbers figure 20-1. device numbering system table 20-1. order numbers mc order number (1) 1. fu = quad flat pack b = shrink dual in-line package operating temperature range 68HC908MR16cfu 68HC908MR16vfu ?40 c to +85 c ?40 c to +105 c 68HC908MR16cb 68HC908MR16vb ?40 c to +85 c ?40 c to +105 c 68hc908mr32cfu 68hc908mr32vfu ?40 c to +85 c ?40 c to +105 c 68hc908mr32cb 68hc908mr32vb ?40 c to +85 c ?40 c to +105 c m c 6 8 h c 9 0 8 m r 3 2 x x x family package designator temperature range f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information and mechanical specifications data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 302 ordering information and mechanical specifications motorola 20.3 64-pin plastic q uad flat pack (qfp) 32 48 49 64 1 16 17 33 detail c -b- -a- -c- -d- -h- m b a c l s v g h e m l detail a k -h- u q r t w x detail c b b p -a-, -b-, d- detail a j f base metal d n section b-b ! "" # $ $ % # ! " " ! "" & "" ' ! ! $ ! ! ! "" ( ! ! $ ! % # % ! $ ! # ( ( ( ) ' ''( ''( ' ' ( ( ( '( ) ) '( # ' # ( ( ( ) ) ( ( # ' ' # ) ' ' ' f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information and mechanical specifications 56-pin shrink dual in-line package (sdip) mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola ordering information and mechanical specifications 303 20.4 56-pin shrink dual in-line package (sdip) ?a? ?b? ?t? 56 29 128 seating plane j 56 pl d 56 pl s a m 0.25 (0.010) t n f g e s b m 0.25 (0.010) t k c h l m dim min max min max millimeters inches a 2.035 2.065 51.69 52.45 b 0.540 0.560 13.72 14.22 c 0.155 0.200 3.94 5.08 d 0.014 0.022 0.36 0.56 e 0.035 bsc 0.89 bsc f 0.032 0.046 0.81 1.17 g 0.070 bsc 1.778 bsc h 0.300 bsc 7.62 bsc j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.600 bsc 15.24 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.02 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information and mechanical specifications data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 304 ordering information and mechanical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 data sheet motorola mc68HC908MR16 305 data sheet ? mc68hc 908mr32 mc68HC908MR16 appendix a. mc68HC908MR16 the information contained in this docum ent pertains to the mc68HC908MR16 with the exception of that shown in figure a-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908MR16 data sheet mc68hc908mr32 mc68HC908MR16 ? rev. 6.0 306 mc68HC908MR16 motorola $0000 $005f i/o registers ? 96 bytes $0060 $035f ram ? 768 bytes $0360 $7fff unimplemented ? 31,904 bytes $8000 $beff flash ? 16,128 bytes $bf00 $fdff unimplemented ? 16,128 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 reserved $fe05 reserved $fe06 reserved $fe07 reserved $fe08 flash control register (flcr) $fe09 unimplemented $fe0a unimplemented $fe0b unimplemented $fe0c sim break address register high (brkh) $fe0d sim break address register low (brkl) $fe0e sim break flag control register (sbfcr) $fe0f lvi status and control register (lviscr) $fe10 $feff monitor rom ? 240 bytes $ff00 $ff7d unimplemented ? 126 bytes $ff7e flash block protect register (flbpr) $ff7f $ffd1 unimplemented ? 83 bytes $ffd2 $ffff vectors ? 46 bytes figure a-1. mc68HC908MR16 memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc68hc908mr32/d rev. 6.0 11/2003 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in differen t applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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